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annotate lib/MC/MCInstrDesc.cpp @ 124:4fa72497ed5d

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fix
author mir3636
date Thu, 30 Nov 2017 20:04:56 +0900
parents 7d135dc70f03
children c2174574ed3a
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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95
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1 //===------ llvm/MC/MCInstrDesc.cpp- Instruction Descriptors --------------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file defines methods on the MCOperandInfo and MCInstrDesc classes, which
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11 // are used to describe target instructions and their operands.
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12 //
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13 //===----------------------------------------------------------------------===//
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14
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15 #include "llvm/MC/MCInstrDesc.h"
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16 #include "llvm/MC/MCInst.h"
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17 #include "llvm/MC/MCRegisterInfo.h"
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18 #include "llvm/MC/MCSubtargetInfo.h"
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19
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20 using namespace llvm;
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21
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22 bool MCInstrDesc::getDeprecatedInfo(MCInst &MI, const MCSubtargetInfo &STI,
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23 std::string &Info) const {
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24 if (ComplexDeprecationInfo)
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25 return ComplexDeprecationInfo(MI, STI, Info);
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26 if (DeprecatedFeature != -1 && STI.getFeatureBits()[DeprecatedFeature]) {
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27 // FIXME: it would be nice to include the subtarget feature here.
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28 Info = "deprecated";
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29 return true;
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30 }
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31 return false;
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32 }
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33 bool MCInstrDesc::mayAffectControlFlow(const MCInst &MI,
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34 const MCRegisterInfo &RI) const {
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35 if (isBranch() || isCall() || isReturn() || isIndirectBranch())
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36 return true;
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37 unsigned PC = RI.getProgramCounter();
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38 if (PC == 0)
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39 return false;
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40 if (hasDefOfPhysReg(MI, PC, RI))
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41 return true;
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42 // A variadic instruction may define PC in the variable operand list.
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43 // There's currently no indication of which entries in a variable
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44 // list are defs and which are uses. While that's the case, this function
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45 // needs to assume they're defs in order to be conservatively correct.
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46 for (int i = NumOperands, e = MI.getNumOperands(); i != e; ++i) {
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47 if (MI.getOperand(i).isReg() &&
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48 RI.isSubRegisterEq(PC, MI.getOperand(i).getReg()))
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49 return true;
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50 }
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51 return false;
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52 }
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53
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54 bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg,
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55 const MCRegisterInfo *MRI) const {
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56 if (const MCPhysReg *ImpDefs = ImplicitDefs)
95
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57 for (; *ImpDefs; ++ImpDefs)
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58 if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
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59 return true;
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60 return false;
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61 }
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62
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63 bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
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64 const MCRegisterInfo &RI) const {
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65 for (int i = 0, e = NumDefs; i != e; ++i)
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66 if (MI.getOperand(i).isReg() &&
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67 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
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68 return true;
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69 return hasImplicitDefOfPhysReg(Reg, &RI);
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70 }