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annotate lib/Target/NVPTX/NVPTXInstrInfo.cpp @ 124:4fa72497ed5d

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fix
author mir3636
date Thu, 30 Nov 2017 20:04:56 +0900
parents 803732b1fca8
children c2174574ed3a
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1 //===- NVPTXInstrInfo.cpp - NVPTX Instruction Information -----------------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file contains the NVPTX implementation of the TargetInstrInfo class.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #include "NVPTXInstrInfo.h"
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15 #include "NVPTX.h"
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16 #include "NVPTXTargetMachine.h"
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17 #include "llvm/ADT/STLExtras.h"
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18 #include "llvm/CodeGen/MachineFunction.h"
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19 #include "llvm/CodeGen/MachineInstrBuilder.h"
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20 #include "llvm/CodeGen/MachineRegisterInfo.h"
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21 #include "llvm/IR/Function.h"
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22
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23 using namespace llvm;
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24
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25 #define GET_INSTRINFO_CTOR_DTOR
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26 #include "NVPTXGenInstrInfo.inc"
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27
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28 // Pin the vtable to this file.
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29 void NVPTXInstrInfo::anchor() {}
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30
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31 NVPTXInstrInfo::NVPTXInstrInfo() : NVPTXGenInstrInfo(), RegInfo() {}
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32
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33 void NVPTXInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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34 MachineBasicBlock::iterator I,
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35 const DebugLoc &DL, unsigned DestReg,
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36 unsigned SrcReg, bool KillSrc) const {
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37 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
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38 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
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39 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
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40
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41 if (RegInfo.getRegSizeInBits(*DestRC) != RegInfo.getRegSizeInBits(*SrcRC))
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42 report_fatal_error("Copy one register into another with a different width");
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43
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44 unsigned Op;
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45 if (DestRC == &NVPTX::Int1RegsRegClass) {
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46 Op = NVPTX::IMOV1rr;
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47 } else if (DestRC == &NVPTX::Int16RegsRegClass) {
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48 Op = NVPTX::IMOV16rr;
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49 } else if (DestRC == &NVPTX::Int32RegsRegClass) {
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50 Op = (SrcRC == &NVPTX::Int32RegsRegClass ? NVPTX::IMOV32rr
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51 : NVPTX::BITCONVERT_32_F2I);
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52 } else if (DestRC == &NVPTX::Int64RegsRegClass) {
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53 Op = (SrcRC == &NVPTX::Int64RegsRegClass ? NVPTX::IMOV64rr
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54 : NVPTX::BITCONVERT_64_F2I);
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55 } else if (DestRC == &NVPTX::Float16RegsRegClass) {
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56 Op = (SrcRC == &NVPTX::Float16RegsRegClass ? NVPTX::FMOV16rr
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57 : NVPTX::BITCONVERT_16_I2F);
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58 } else if (DestRC == &NVPTX::Float16x2RegsRegClass) {
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59 Op = NVPTX::IMOV32rr;
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60 } else if (DestRC == &NVPTX::Float32RegsRegClass) {
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61 Op = (SrcRC == &NVPTX::Float32RegsRegClass ? NVPTX::FMOV32rr
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62 : NVPTX::BITCONVERT_32_I2F);
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63 } else if (DestRC == &NVPTX::Float64RegsRegClass) {
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64 Op = (SrcRC == &NVPTX::Float64RegsRegClass ? NVPTX::FMOV64rr
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65 : NVPTX::BITCONVERT_64_I2F);
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66 } else {
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67 llvm_unreachable("Bad register copy");
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68 }
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69 BuildMI(MBB, I, DL, get(Op), DestReg)
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70 .addReg(SrcReg, getKillRegState(KillSrc));
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71 }
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72
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73 bool NVPTXInstrInfo::isMoveInstr(const MachineInstr &MI, unsigned &SrcReg,
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74 unsigned &DestReg) const {
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75 // Look for the appropriate part of TSFlags
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76 bool isMove = false;
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77
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78 unsigned TSFlags =
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79 (MI.getDesc().TSFlags & NVPTX::SimpleMoveMask) >> NVPTX::SimpleMoveShift;
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80 isMove = (TSFlags == 1);
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81
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82 if (isMove) {
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83 MachineOperand dest = MI.getOperand(0);
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84 MachineOperand src = MI.getOperand(1);
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85 assert(dest.isReg() && "dest of a movrr is not a reg");
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86 assert(src.isReg() && "src of a movrr is not a reg");
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87
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88 SrcReg = src.getReg();
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89 DestReg = dest.getReg();
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90 return true;
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91 }
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92
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93 return false;
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94 }
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96 bool NVPTXInstrInfo::isLoadInstr(const MachineInstr &MI,
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97 unsigned &AddrSpace) const {
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98 bool isLoad = false;
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99 unsigned TSFlags =
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100 (MI.getDesc().TSFlags & NVPTX::isLoadMask) >> NVPTX::isLoadShift;
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101 isLoad = (TSFlags == 1);
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102 if (isLoad)
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103 AddrSpace = getLdStCodeAddrSpace(MI);
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104 return isLoad;
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105 }
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106
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107 bool NVPTXInstrInfo::isStoreInstr(const MachineInstr &MI,
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108 unsigned &AddrSpace) const {
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109 bool isStore = false;
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110 unsigned TSFlags =
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111 (MI.getDesc().TSFlags & NVPTX::isStoreMask) >> NVPTX::isStoreShift;
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112 isStore = (TSFlags == 1);
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113 if (isStore)
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114 AddrSpace = getLdStCodeAddrSpace(MI);
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115 return isStore;
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116 }
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117
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118 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
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119 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
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120 /// implemented for a target). Upon success, this returns false and returns
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121 /// with the following information in various cases:
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122 ///
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123 /// 1. If this block ends with no branches (it just falls through to its succ)
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124 /// just return false, leaving TBB/FBB null.
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125 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
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126 /// the destination block.
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127 /// 3. If this block ends with an conditional branch and it falls through to
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128 /// an successor block, it sets TBB to be the branch destination block and a
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129 /// list of operands that evaluate the condition. These
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
130 /// operands can be passed to other TargetInstrInfo methods to create new
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
131 /// branches.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
132 /// 4. If this block ends with an conditional branch and an unconditional
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
133 /// block, it returns the 'true' destination in TBB, the 'false' destination
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
134 /// in FBB, and a list of operands that evaluate the condition. These
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
135 /// operands can be passed to other TargetInstrInfo methods to create new
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
136 /// branches.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
137 ///
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
138 /// Note that removeBranch and insertBranch must be implemented to support
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
139 /// cases where this method returns success.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
140 ///
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
141 bool NVPTXInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
1172e4bd9c6f update 4.0.0
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parents: 100
diff changeset
142 MachineBasicBlock *&TBB,
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
143 MachineBasicBlock *&FBB,
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
144 SmallVectorImpl<MachineOperand> &Cond,
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
145 bool AllowModify) const {
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
146 // If the block has no terminators, it just falls into the block after it.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
147 MachineBasicBlock::iterator I = MBB.end();
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
148 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I))
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
149 return false;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
150
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
151 // Get the last instruction in the block.
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
152 MachineInstr &LastInst = *I;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
153
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
154 // If there is only one terminator instruction, process it.
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
155 if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
156 if (LastInst.getOpcode() == NVPTX::GOTO) {
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
157 TBB = LastInst.getOperand(0).getMBB();
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
158 return false;
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
159 } else if (LastInst.getOpcode() == NVPTX::CBranch) {
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
160 // Block ends with fall-through condbranch.
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
161 TBB = LastInst.getOperand(1).getMBB();
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
162 Cond.push_back(LastInst.getOperand(0));
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
163 return false;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
164 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
165 // Otherwise, don't know what this is.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
166 return true;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
167 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
168
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
169 // Get the instruction before it if it's a terminator.
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
170 MachineInstr &SecondLastInst = *I;
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
171
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
172 // If there are three terminators, we don't know what sort of block this is.
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
173 if (I != MBB.begin() && isUnpredicatedTerminator(*--I))
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
174 return true;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
175
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
176 // If the block ends with NVPTX::GOTO and NVPTX:CBranch, handle it.
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
177 if (SecondLastInst.getOpcode() == NVPTX::CBranch &&
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
178 LastInst.getOpcode() == NVPTX::GOTO) {
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
179 TBB = SecondLastInst.getOperand(1).getMBB();
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
180 Cond.push_back(SecondLastInst.getOperand(0));
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
181 FBB = LastInst.getOperand(0).getMBB();
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
182 return false;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
183 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
184
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
185 // If the block ends with two NVPTX:GOTOs, handle it. The second one is not
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
186 // executed, so remove it.
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
187 if (SecondLastInst.getOpcode() == NVPTX::GOTO &&
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
188 LastInst.getOpcode() == NVPTX::GOTO) {
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
189 TBB = SecondLastInst.getOperand(0).getMBB();
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
190 I = LastInst;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
191 if (AllowModify)
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
192 I->eraseFromParent();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
193 return false;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
194 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
195
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
196 // Otherwise, can't handle this.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
197 return true;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
198 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
199
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
200 unsigned NVPTXInstrInfo::removeBranch(MachineBasicBlock &MBB,
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
201 int *BytesRemoved) const {
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
202 assert(!BytesRemoved && "code size not handled");
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
203 MachineBasicBlock::iterator I = MBB.end();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
204 if (I == MBB.begin())
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
205 return 0;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
206 --I;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
207 if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() != NVPTX::CBranch)
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
208 return 0;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
209
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
210 // Remove the branch.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
211 I->eraseFromParent();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
212
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
213 I = MBB.end();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
214
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
215 if (I == MBB.begin())
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
216 return 1;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
217 --I;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
218 if (I->getOpcode() != NVPTX::CBranch)
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
219 return 1;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
220
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
221 // Remove the branch.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
222 I->eraseFromParent();
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
223 return 2;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
224 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
225
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
226 unsigned NVPTXInstrInfo::insertBranch(MachineBasicBlock &MBB,
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
227 MachineBasicBlock *TBB,
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
228 MachineBasicBlock *FBB,
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
229 ArrayRef<MachineOperand> Cond,
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
230 const DebugLoc &DL,
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
231 int *BytesAdded) const {
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
232 assert(!BytesAdded && "code size not handled");
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
233
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
234 // Shouldn't be a fall through.
120
1172e4bd9c6f update 4.0.0
mir3636
parents: 100
diff changeset
235 assert(TBB && "insertBranch must not be told to insert a fallthrough");
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
236 assert((Cond.size() == 1 || Cond.size() == 0) &&
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
237 "NVPTX branch conditions have two components!");
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
238
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
239 // One-way branch.
77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
diff changeset
240 if (!FBB) {
0
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
241 if (Cond.empty()) // Unconditional branch
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
242 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
243 else // Conditional branch
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
244 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg())
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
245 .addMBB(TBB);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
246 return 1;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
247 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
248
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
249 // Two-way Conditional Branch.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
250 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
251 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(FBB);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
252 return 2;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
253 }