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1 //===-- RISCV.td - Describe the RISCV Target Machine -------*- tablegen -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9
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10 include "llvm/Target/Target.td"
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11
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121
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12 //===----------------------------------------------------------------------===//
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13 // RISC-V subtarget features and instruction predicates.
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14 //===----------------------------------------------------------------------===//
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15
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16 def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true",
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17 "Implements RV64">;
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18
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19 def RV64 : HwMode<"+64bit">;
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20 def RV32 : HwMode<"-64bit">;
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21
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22 //===----------------------------------------------------------------------===//
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23 // Registers, calling conventions, instruction descriptions.
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24 //===----------------------------------------------------------------------===//
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25
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120
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26 include "RISCVRegisterInfo.td"
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121
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27 include "RISCVCallingConv.td"
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120
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28 include "RISCVInstrInfo.td"
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29
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121
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30 //===----------------------------------------------------------------------===//
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31 // RISC-V processors supported.
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32 //===----------------------------------------------------------------------===//
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33
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34 def : ProcessorModel<"generic-rv32", NoSchedModel, []>;
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35
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36 def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
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37
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121
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38 //===----------------------------------------------------------------------===//
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39 // Define the RISC-V target.
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40 //===----------------------------------------------------------------------===//
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41
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42 def RISCVInstrInfo : InstrInfo {
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43 // TODO: disable guessInstructionProperties when
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44 // https://reviews.llvm.org/D37065 lands.
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45 let guessInstructionProperties = 1;
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46 }
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47
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48 def RISCVAsmParser : AsmParser {
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49 let ShouldEmitMatchRegisterAltName = 1;
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50 }
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51
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120
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52 def RISCV : Target {
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53 let InstructionSet = RISCVInstrInfo;
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121
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54 let AssemblyParsers = [RISCVAsmParser];
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55 }
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