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annotate lib/Target/X86/X86InstrMPX.td @ 124:4fa72497ed5d

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fix
author mir3636
date Thu, 30 Nov 2017 20:04:56 +0900
parents 803732b1fca8
children 3a76565eade5
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1 //===-- X86InstrMPX.td - MPX Instruction Set ---------*- tablegen -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file describes the X86 MPX instruction set, defining the
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11 // instructions, and properties of the instructions which are needed for code
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12 // generation, machine code emission, and analysis.
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13 //
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14 //===----------------------------------------------------------------------===//
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15
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16 multiclass mpx_bound_make<bits<8> opc, string OpcodeStr> {
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17 let mayLoad = 1 in {
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18 def 32rm: I<opc, MRMSrcMem, (outs BNDR:$dst), (ins i32mem:$src),
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19 OpcodeStr#"\t{$src, $dst|$dst, $src}", []>,
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20 Requires<[HasMPX, Not64BitMode]>;
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21 def 64rm: RI<opc, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src),
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22 OpcodeStr#"\t{$src, $dst|$dst, $src}", []>,
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23 Requires<[HasMPX, In64BitMode]>;
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24 }
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25 }
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26
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27 defm BNDMK : mpx_bound_make<0x1B, "bndmk">, XS;
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28
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29 multiclass mpx_bound_check<bits<8> opc, string OpcodeStr> {
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30 let mayLoad = 1 in {
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31 def 32rm: I<opc, MRMSrcMem, (outs), (ins BNDR:$src1, i32mem:$src2),
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32 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
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33 Requires<[HasMPX, Not64BitMode]>;
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34 def 64rm: RI<opc, MRMSrcMem, (outs), (ins BNDR:$src1, i64mem:$src2),
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35 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
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36 Requires<[HasMPX, In64BitMode]>;
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37 }
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38 def 32rr: I<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR32:$src2),
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39 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
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40 Requires<[HasMPX, Not64BitMode]>;
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41 def 64rr: RI<opc, MRMSrcReg, (outs), (ins BNDR:$src1, GR64:$src2),
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42 OpcodeStr#"\t{$src2, $src1|$src1, $src2}", []>,
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43 Requires<[HasMPX, In64BitMode]>;
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44 }
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45 defm BNDCL : mpx_bound_check<0x1A, "bndcl">, XS;
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46 defm BNDCU : mpx_bound_check<0x1A, "bndcu">, XD;
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47 defm BNDCN : mpx_bound_check<0x1B, "bndcn">, XD;
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48
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49 def BNDMOVRMrr : I<0x1A, MRMSrcReg, (outs BNDR:$dst), (ins BNDR:$src),
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50 "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
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51 Requires<[HasMPX]>;
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52 let mayLoad = 1 in {
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53 def BNDMOVRM32rm : I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src),
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54 "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
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55 Requires<[HasMPX, Not64BitMode]>;
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56 def BNDMOVRM64rm : RI<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i128mem:$src),
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57 "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
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58 Requires<[HasMPX, In64BitMode]>;
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59 }
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60 def BNDMOVMRrr : I<0x1B, MRMDestReg, (outs BNDR:$dst), (ins BNDR:$src),
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61 "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
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62 Requires<[HasMPX]>;
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63 let mayStore = 1 in {
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64 def BNDMOVMR32mr : I<0x1B, MRMDestMem, (outs), (ins i64mem:$dst, BNDR:$src),
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65 "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
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66 Requires<[HasMPX, Not64BitMode]>;
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67 def BNDMOVMR64mr : RI<0x1B, MRMDestMem, (outs), (ins i128mem:$dst, BNDR:$src),
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68 "bndmov\t{$src, $dst|$dst, $src}", []>, PD,
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69 Requires<[HasMPX, In64BitMode]>;
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71 def BNDSTXmr: I<0x1B, MRMDestMem, (outs), (ins i64mem:$dst, BNDR:$src),
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72 "bndstx\t{$src, $dst|$dst, $src}", []>, PS,
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73 Requires<[HasMPX]>;
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74 }
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75 let mayLoad = 1 in
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76 def BNDLDXrm: I<0x1A, MRMSrcMem, (outs BNDR:$dst), (ins i64mem:$src),
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77 "bndldx\t{$src, $dst|$dst, $src}", []>, PS,
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78 Requires<[HasMPX]>;