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report error when code segment's tail call flag was changed false
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Sun, 06 Oct 2013 00:17:31 +0900
parents 9ad51c7bc036
children
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1 ======================
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2 LLVM 3.3 Release Notes
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3 ======================
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5 .. contents::
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6 :local:
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7
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8 .. warning::
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9 These are in-progress notes for the upcoming LLVM 3.3 release. You may
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10 prefer the `LLVM 3.2 Release Notes <http://llvm.org/releases/3.2/docs
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11 /ReleaseNotes.html>`_.
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14 Introduction
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15 ============
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16
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17 This document contains the release notes for the LLVM Compiler Infrastructure,
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18 release 3.3. Here we describe the status of LLVM, including major improvements
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19 from the previous release, improvements in various subprojects of LLVM, and
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20 some of the current users of the code. All LLVM releases may be downloaded
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21 from the `LLVM releases web site <http://llvm.org/releases/>`_.
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22
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23 For more information about LLVM, including information about the latest
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24 release, please check out the `main LLVM web site <http://llvm.org/>`_. If you
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25 have questions or comments, the `LLVM Developer's Mailing List
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26 <http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev>`_ is a good place to send
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27 them.
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28
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29 Note that if you are reading this file from a Subversion checkout or the main
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30 LLVM web page, this document applies to the *next* release, not the current
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31 one. To see the release notes for a specific release, please see the `releases
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32 page <http://llvm.org/releases/>`_.
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33
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34 Non-comprehensive list of changes in this release
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35 =================================================
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36
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37 .. NOTE
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38 For small 1-3 sentence descriptions, just add an entry at the end of
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39 this list. If your description won't fit comfortably in one bullet
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40 point (e.g. maybe you would like to give an example of the
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41 functionality, or simply have a lot to talk about), see the `NOTE` below
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42 for adding a new subsection.
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43
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44 * The CellSPU port has been removed. It can still be found in older versions.
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45
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46 * The IR-level extended linker APIs (for example, to link bitcode files out of
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47 archives) have been removed. Any existing clients of these features should
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48 move to using a linker with integrated LTO support.
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49
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50 * LLVM and Clang's documentation has been migrated to the `Sphinx
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51 <http://sphinx-doc.org/>`_ documentation generation system which uses
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52 easy-to-write reStructuredText. See `llvm/docs/README.txt` for more
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53 information.
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54
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55 * TargetTransformInfo (TTI) is a new interface that can be used by IR-level
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56 passes to obtain target-specific information, such as the costs of
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57 instructions. Only "Lowering" passes such as LSR and the vectorizer are
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58 allowed to use the TTI infrastructure.
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59
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60 * We've improved the X86 and ARM cost model.
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61
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62 * The Attributes classes have been completely rewritten and expanded. They now
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63 support not only enumerated attributes and alignments, but "string"
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64 attributes, which are useful for passing information to code generation. See
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65 :doc:`HowToUseAttributes` for more details.
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66
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67 * TableGen's syntax for instruction selection patterns has been simplified.
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68 Instead of specifying types indirectly with register classes, you should now
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69 specify types directly in the input patterns. See ``SparcInstrInfo.td`` for
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70 examples of the new syntax. The old syntax using register classes still
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71 works, but it will be removed in a future LLVM release.
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72
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73 * MCJIT now supports exception handling. Support for it in the old jit will be
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74 removed in the 3.4 release.
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75
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76 * Command line options can now be grouped into categories which are shown in
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77 the output of ``-help``. See :ref:`grouping options into categories`.
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78
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79 * The appearance of command line options in ``-help`` that are inherited by
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80 linking with libraries that use the LLVM Command line support library can now
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81 be modified at runtime. See :ref:`cl::getRegisteredOptions`.
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82
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83 * ... next change ...
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84
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85 .. NOTE
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86 If you would like to document a larger change, then you can add a
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87 subsection about it right here. You can copy the following boilerplate
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88 and un-indent it (the indentation causes it to be inside this comment).
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89
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90 Special New Feature
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91 -------------------
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92
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93 Makes programs 10x faster by doing Special New Thing.
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94
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95 AArch64 target
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96 --------------
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97
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98 We've added support for AArch64, ARM's 64-bit architecture. Development is still
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99 in fairly early stages, but we expect successful compilation when:
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100
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101 - compiling standard compliant C99 and C++03 with Clang;
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102 - using Linux as a target platform;
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103 - where code + static data doesn't exceed 4GB in size (heap allocated data has
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104 no limitation).
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105
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106 Some additional functionality is also implemented, notably DWARF debugging,
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107 GNU-style thread local storage and inline assembly.
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108
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109 Hexagon Target
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110 --------------
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111
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112 - Removed support for legacy hexagonv2 and hexagonv3 processor
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113 architectures which are no longer in use. Currently supported
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114 architectures are hexagonv4 and hexagonv5.
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115
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116 Loop Vectorizer
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117 ---------------
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118
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119 We've continued the work on the loop vectorizer. The loop vectorizer now
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120 has the following features:
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121
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122 - Loops with unknown trip counts.
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123 - Runtime checks of pointers.
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124 - Reductions, Inductions.
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125 - Min/Max reductions of integers.
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126 - If Conversion.
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127 - Pointer induction variables.
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128 - Reverse iterators.
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129 - Vectorization of mixed types.
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130 - Vectorization of function calls.
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131 - Partial unrolling during vectorization.
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132
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133 The loop vectorizer is now enabled by default for -O3.
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134
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135 SLP Vectorizer
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136 --------------
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137
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138 LLVM now has a new SLP vectorizer. The new SLP vectorizer is not enabled by
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139 default but can be enabled using the clang flag -fslp-vectorize. The BB-vectorizer
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140 can also be enabled using the command line flag -fslp-vectorize-aggressive.
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141
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142 R600 Backend
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143 ------------
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144
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145 The R600 backend was added in this release, it supports AMD GPUs
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146 (HD2XXX - HD7XXX). This backend is used in AMD's Open Source
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147 graphics / compute drivers which are developed as part of the `Mesa3D
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148 <http://www.mesa3d.org>`_ project.
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149
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150 SystemZ/s390x Backend
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151 ---------------------
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152
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153 LLVM and clang now support IBM's z/Architecture. At present this support
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154 is restricted to GNU/Linux (GNU triplet s390x-linux-gnu) and requires
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155 z10 or greater.
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156
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157
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158 External Open Source Projects Using LLVM 3.3
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159 ============================================
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160
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161 An exciting aspect of LLVM is that it is used as an enabling technology for
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162 a lot of other language and tools projects. This section lists some of the
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163 projects that have already been updated to work with LLVM 3.3.
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164
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165
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166 Portable Computing Language (pocl)
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167 ----------------------------------
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168
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169 In addition to producing an easily portable open source OpenCL
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170 implementation, another major goal of `pocl <http://pocl.sourceforge.net/>`_
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171 is improving performance portability of OpenCL programs with
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172 compiler optimizations, reducing the need for target-dependent manual
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173 optimizations. An important part of pocl is a set of LLVM passes used to
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174 statically parallelize multiple work-items with the kernel compiler, even in
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175 the presence of work-group barriers. This enables static parallelization of
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176 the fine-grained static concurrency in the work groups in multiple ways.
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177
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178 TTA-based Co-design Environment (TCE)
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179 -------------------------------------
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180
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181 `TCE <http://tce.cs.tut.fi/>`_ is a toolset for designing new
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182 processors based on the Transport triggered architecture (TTA).
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183 The toolset provides a complete co-design flow from C/C++
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184 programs down to synthesizable VHDL/Verilog and parallel program binaries.
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185 Processor customization points include the register files, function units,
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186 supported operations, and the interconnection network.
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187
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188 TCE uses Clang and LLVM for C/C++/OpenCL C language support, target independent
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189 optimizations and also for parts of code generation. It generates new
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190 LLVM-based code generators "on the fly" for the designed TTA processors and
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191 loads them in to the compiler backend as runtime libraries to avoid
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192 per-target recompilation of larger parts of the compiler chain.
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193
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194
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195 Additional Information
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196 ======================
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197
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198 A wide variety of additional information is available on the `LLVM web page
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199 <http://llvm.org/>`_, in particular in the `documentation
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200 <http://llvm.org/docs/>`_ section. The web page also contains versions of the
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201 API documentation which is up-to-date with the Subversion version of the source
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202 code. You can access versions of these documents specific to this release by
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203 going into the ``llvm/docs/`` directory in the LLVM tree.
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204
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205 If you have any questions or comments about LLVM, please feel free to contact
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206 us via the `mailing lists <http://llvm.org/docs/#maillist>`_.
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207