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annotate test/MC/Disassembler/ARM/invalid-thumb-MSR-MClass.txt @ 85:5e5d649e25d2

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Update LLVM 3.7
author Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
date Thu, 19 Feb 2015 15:19:25 +0900
parents 54457678186b
children 1172e4bd9c6f
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1 # RUN: not llvm-mc -disassemble %s -triple=thumbv7em 2>&1 | FileCheck --check-prefix=CHECK %s
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2 # RUN: not llvm-mc -disassemble %s -triple=thumbv7m 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7M %s
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4 #------------------------------------------------------------------------------
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5 # Undefined encodings for mrs
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6 #------------------------------------------------------------------------------
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8 # invalid SYSm
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9 # CHECK: warning: invalid instruction encoding
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10 # CHECK-NEXT: [0xef 0xf3 0x80 0x80]
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11 [0xef 0xf3 0x80 0x80]
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12
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13 #------------------------------------------------------------------------------
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14 # Undefined encodings for msr
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15 #------------------------------------------------------------------------------
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16
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17 # invalid mask = '00'
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18 # CHECK: warning: potentially undefined instruction encoding
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19 # CHECK-NEXT: [0x80 0xf3 0x00 0x80]
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20 [0x80 0xf3 0x00 0x80]
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22 # invalid mask = '11' with SYSm not in {0..3}
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23 # CHECK: warning: potentially undefined instruction encoding
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24 # CHECK-NEXT: [0x80 0xf3 0x05 0x8c]
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25 [0x80 0xf3 0x05 0x8c]
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27 # invalid mask = '01' (ThumbV7M does not have the DSP extension)
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28 # CHECK-V7M: warning: potentially undefined instruction encoding
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29 # CHECK-V7M-NEXT: [0x80 0xf3 0x00 0x84]
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30 [0x80 0xf3 0x00 0x84]
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31
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32 # invalid SYSm
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33 # CHECK: warning: invalid instruction encoding
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34 # CHECK-NEXT: [0x80 0xf3 0x80 0x88]
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35 [0x80 0xf3 0x80 0x88]