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221
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1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=SI-NOHSA,GCN-NOHSA,FUNC %s
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2 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=VI-NOHSA,GCN-NOHSA,FUNC %s
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3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefixes=EG,FUNC %s
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150
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4
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5 ; Legacy intrinsics that just read implicit parameters
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6
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7 ; FUNC-LABEL: {{^}}ngroups_x:
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8 ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x0
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9 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x0
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10 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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11 ; GCN-NOHSA: buffer_store_dword [[VVAL]]
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12
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13 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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14 ; EG: MOV {{\*? *}}[[VAL]], KC0[0].X
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15 define amdgpu_kernel void @ngroups_x (i32 addrspace(1)* %out) {
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16 entry:
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17 %0 = call i32 @llvm.r600.read.ngroups.x() #0
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18 store i32 %0, i32 addrspace(1)* %out
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19 ret void
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20 }
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21
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22 ; FUNC-LABEL: {{^}}ngroups_y:
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23 ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x1
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24 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x4
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25 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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26 ; GCN-NOHSA: buffer_store_dword [[VVAL]]
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27
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28 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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29 ; EG: MOV {{\*? *}}[[VAL]], KC0[0].Y
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30 define amdgpu_kernel void @ngroups_y (i32 addrspace(1)* %out) {
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31 entry:
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32 %0 = call i32 @llvm.r600.read.ngroups.y() #0
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33 store i32 %0, i32 addrspace(1)* %out
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34 ret void
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35 }
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36
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37 ; FUNC-LABEL: {{^}}ngroups_z:
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38 ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x2
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39 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x8
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40 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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41 ; GCN-NOHSA: buffer_store_dword [[VVAL]]
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42
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43 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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44 ; EG: MOV {{\*? *}}[[VAL]], KC0[0].Z
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45 define amdgpu_kernel void @ngroups_z (i32 addrspace(1)* %out) {
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46 entry:
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47 %0 = call i32 @llvm.r600.read.ngroups.z() #0
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48 store i32 %0, i32 addrspace(1)* %out
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49 ret void
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50 }
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51
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52 ; FUNC-LABEL: {{^}}global_size_x:
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53 ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x3
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54 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0xc
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55 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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56 ; GCN-NOHSA: buffer_store_dword [[VVAL]]
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57
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58 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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59 ; EG: MOV {{\*? *}}[[VAL]], KC0[0].W
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60 define amdgpu_kernel void @global_size_x (i32 addrspace(1)* %out) {
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61 entry:
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62 %0 = call i32 @llvm.r600.read.global.size.x() #0
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63 store i32 %0, i32 addrspace(1)* %out
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64 ret void
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65 }
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66
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67 ; FUNC-LABEL: {{^}}global_size_y:
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68 ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x4
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69 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x10
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70 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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71 ; GCN-NOHSA: buffer_store_dword [[VVAL]]
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72
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73 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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74 ; EG: MOV {{\*? *}}[[VAL]], KC0[1].X
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75 define amdgpu_kernel void @global_size_y (i32 addrspace(1)* %out) {
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76 entry:
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77 %0 = call i32 @llvm.r600.read.global.size.y() #0
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78 store i32 %0, i32 addrspace(1)* %out
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79 ret void
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80 }
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81
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82 ; FUNC-LABEL: {{^}}global_size_z:
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83 ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x5
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84 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x14
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85 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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86 ; GCN-NOHSA: buffer_store_dword [[VVAL]]
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87
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88 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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89 ; EG: MOV {{\*? *}}[[VAL]], KC0[1].Y
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90 define amdgpu_kernel void @global_size_z (i32 addrspace(1)* %out) {
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91 entry:
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92 %0 = call i32 @llvm.r600.read.global.size.z() #0
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93 store i32 %0, i32 addrspace(1)* %out
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94 ret void
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95 }
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96
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97 ; FUNC-LABEL: {{^}}local_size_x:
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98 ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x6
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99 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x18
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100 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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101 ; GCN-NOHSA: buffer_store_dword [[VVAL]]
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102
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103 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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104 ; EG: MOV {{\*? *}}[[VAL]], KC0[1].Z
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105 define amdgpu_kernel void @local_size_x (i32 addrspace(1)* %out) {
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106 entry:
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107 %0 = call i32 @llvm.r600.read.local.size.x() #0
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108 store i32 %0, i32 addrspace(1)* %out
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109 ret void
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110 }
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111
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112 ; FUNC-LABEL: {{^}}local_size_y:
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113 ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x7
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114 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x1c
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115 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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116 ; GCN-NOHSA: buffer_store_dword [[VVAL]]
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117
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118 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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119 ; EG: MOV {{\*? *}}[[VAL]], KC0[1].W
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120 define amdgpu_kernel void @local_size_y (i32 addrspace(1)* %out) {
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121 entry:
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122 %0 = call i32 @llvm.r600.read.local.size.y() #0
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123 store i32 %0, i32 addrspace(1)* %out
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124 ret void
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125 }
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126
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127 ; FUNC-LABEL: {{^}}local_size_z:
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128 ; SI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x8
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129 ; VI-NOHSA: s_load_dword [[VAL:s[0-9]+]], s[0:1], 0x20
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130 ; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], [[VAL]]
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131 ; GCN-NOHSA: buffer_store_dword [[VVAL]]
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132
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133 ; EG: MEM_RAT_CACHELESS STORE_RAW [[VAL:T[0-9]+\.X]]
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134 ; EG: MOV {{\*? *}}[[VAL]], KC0[2].X
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135 define amdgpu_kernel void @local_size_z (i32 addrspace(1)* %out) {
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136 entry:
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137 %0 = call i32 @llvm.r600.read.local.size.z() #0
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138 store i32 %0, i32 addrspace(1)* %out
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139 ret void
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140 }
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141
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142 declare i32 @llvm.r600.read.ngroups.x() #0
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143 declare i32 @llvm.r600.read.ngroups.y() #0
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144 declare i32 @llvm.r600.read.ngroups.z() #0
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145
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146 declare i32 @llvm.r600.read.global.size.x() #0
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147 declare i32 @llvm.r600.read.global.size.y() #0
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148 declare i32 @llvm.r600.read.global.size.z() #0
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149
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150 declare i32 @llvm.r600.read.local.size.x() #0
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151 declare i32 @llvm.r600.read.local.size.y() #0
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152 declare i32 @llvm.r600.read.local.size.z() #0
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153
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154 attributes #0 = { readnone }
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