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1 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=SI,FUNC %s
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2 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefixes=VI,FUNC %s
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3 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck --check-prefixes=R600,FUNC %s
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150
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4
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5 ; FUNC-LABEL: {{^}}fneg_fabs_fadd_f32:
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6 ; SI-NOT: and
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7 ; SI: v_sub_f32_e64 {{v[0-9]+}}, {{s[0-9]+}}, |{{v[0-9]+}}|
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8 define amdgpu_kernel void @fneg_fabs_fadd_f32(float addrspace(1)* %out, float %x, float %y) {
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9 %fabs = call float @llvm.fabs.f32(float %x)
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10 %fsub = fsub float -0.000000e+00, %fabs
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11 %fadd = fadd float %y, %fsub
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12 store float %fadd, float addrspace(1)* %out, align 4
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13 ret void
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14 }
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15
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16 ; FUNC-LABEL: {{^}}fneg_fabs_fmul_f32:
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17 ; SI-NOT: and
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18 ; SI: v_mul_f32_e64 {{v[0-9]+}}, {{s[0-9]+}}, -|{{v[0-9]+}}|
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19 ; SI-NOT: and
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20 define amdgpu_kernel void @fneg_fabs_fmul_f32(float addrspace(1)* %out, float %x, float %y) {
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21 %fabs = call float @llvm.fabs.f32(float %x)
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22 %fsub = fsub float -0.000000e+00, %fabs
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23 %fmul = fmul float %y, %fsub
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24 store float %fmul, float addrspace(1)* %out, align 4
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25 ret void
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26 }
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27
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28 ; DAGCombiner will transform:
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29 ; (fabs (f32 bitcast (i32 a))) => (f32 bitcast (and (i32 a), 0x7FFFFFFF))
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30 ; unless isFabsFree returns true
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31
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32 ; FUNC-LABEL: {{^}}fneg_fabs_free_f32:
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33 ; R600-NOT: AND
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34 ; R600: |PV.{{[XYZW]}}|
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35 ; R600: -PV
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36
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37 ; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
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38 ; VI: s_bitset1_b32 s{{[0-9]+}}, 31
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39 define amdgpu_kernel void @fneg_fabs_free_f32(float addrspace(1)* %out, i32 %in) {
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40 %bc = bitcast i32 %in to float
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41 %fabs = call float @llvm.fabs.f32(float %bc)
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42 %fsub = fsub float -0.000000e+00, %fabs
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43 store float %fsub, float addrspace(1)* %out
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44 ret void
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45 }
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46
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47 ; FUNC-LABEL: {{^}}fneg_fabs_fn_free_f32:
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48 ; R600-NOT: AND
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49 ; R600: |PV.{{[XYZW]}}|
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50 ; R600: -PV
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51
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52 ; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
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53 define amdgpu_kernel void @fneg_fabs_fn_free_f32(float addrspace(1)* %out, i32 %in) {
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54 %bc = bitcast i32 %in to float
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55 %fabs = call float @fabs(float %bc)
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56 %fsub = fsub float -0.000000e+00, %fabs
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57 store float %fsub, float addrspace(1)* %out
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58 ret void
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59 }
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60
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61 ; FUNC-LABEL: {{^}}fneg_fabs_f32:
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62 ; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
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63 define amdgpu_kernel void @fneg_fabs_f32(float addrspace(1)* %out, float %in) {
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64 %fabs = call float @llvm.fabs.f32(float %in)
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65 %fsub = fsub float -0.000000e+00, %fabs
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66 store float %fsub, float addrspace(1)* %out, align 4
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67 ret void
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68 }
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69
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70 ; FUNC-LABEL: {{^}}v_fneg_fabs_f32:
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71 ; SI: v_or_b32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
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72 define amdgpu_kernel void @v_fneg_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
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73 %val = load float, float addrspace(1)* %in, align 4
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74 %fabs = call float @llvm.fabs.f32(float %val)
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75 %fsub = fsub float -0.000000e+00, %fabs
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76 store float %fsub, float addrspace(1)* %out, align 4
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77 ret void
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78 }
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79
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80 ; FUNC-LABEL: {{^}}fneg_fabs_v2f32:
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81 ; R600: |{{(PV|T[0-9])\.[XYZW]}}|
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82 ; R600: -PV
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83 ; R600: |{{(PV|T[0-9])\.[XYZW]}}|
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84 ; R600: -PV
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85
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86 ; FIXME: In this case two uses of the constant should be folded
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87 ; SI: s_brev_b32 [[SIGNBITK:s[0-9]+]], 1{{$}}
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88 ; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, [[SIGNBITK]]
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89 ; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, [[SIGNBITK]]
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90 define amdgpu_kernel void @fneg_fabs_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %in) {
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91 %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %in)
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92 %fsub = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %fabs
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93 store <2 x float> %fsub, <2 x float> addrspace(1)* %out
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94 ret void
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95 }
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96
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97 ; FUNC-LABEL: {{^}}fneg_fabs_v4f32:
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98 ; SI: s_brev_b32 [[SIGNBITK:s[0-9]+]], 1{{$}}
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99 ; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, [[SIGNBITK]]
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100 ; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, [[SIGNBITK]]
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101 ; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, [[SIGNBITK]]
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102 ; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, [[SIGNBITK]]
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103 define amdgpu_kernel void @fneg_fabs_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %in) {
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104 %fabs = call <4 x float> @llvm.fabs.v4f32(<4 x float> %in)
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105 %fsub = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %fabs
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106 store <4 x float> %fsub, <4 x float> addrspace(1)* %out
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107 ret void
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108 }
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109
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110 declare float @fabs(float) readnone
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111 declare float @llvm.fabs.f32(float) readnone
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112 declare <2 x float> @llvm.fabs.v2f32(<2 x float>) readnone
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113 declare <4 x float> @llvm.fabs.v4f32(<4 x float>) readnone
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