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150
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1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI %s
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2
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3 declare i32 @llvm.amdgcn.workitem.id.x() #1
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4 declare { float, i1 } @llvm.amdgcn.div.scale.f32(float, float, i1) #1
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5 declare { double, i1 } @llvm.amdgcn.div.scale.f64(double, double, i1) #1
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6 declare float @llvm.fabs.f32(float) #1
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7
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8 ; SI-LABEL: {{^}}test_div_scale_f32_1:
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9 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
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10 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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11 ; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]
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12 ; SI: buffer_store_dword [[RESULT0]]
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13 ; SI: s_endpgm
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14 define amdgpu_kernel void @test_div_scale_f32_1(float addrspace(1)* %out, float addrspace(1)* %in) nounwind {
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15 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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16 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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17 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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18
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19 %a = load volatile float, float addrspace(1)* %gep.0, align 4
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20 %b = load volatile float, float addrspace(1)* %gep.1, align 4
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21
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22 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 false) nounwind readnone
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23 %result0 = extractvalue { float, i1 } %result, 0
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24 store float %result0, float addrspace(1)* %out, align 4
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25 ret void
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26 }
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27
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28 ; SI-LABEL: {{^}}test_div_scale_f32_2:
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29 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
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30 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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31 ; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]
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32 ; SI: buffer_store_dword [[RESULT0]]
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33 ; SI: s_endpgm
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34 define amdgpu_kernel void @test_div_scale_f32_2(float addrspace(1)* %out, float addrspace(1)* %in) nounwind {
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35 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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36 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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37 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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38
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39 %a = load volatile float, float addrspace(1)* %gep.0, align 4
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40 %b = load volatile float, float addrspace(1)* %gep.1, align 4
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41
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42 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 true) nounwind readnone
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43 %result0 = extractvalue { float, i1 } %result, 0
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44 store float %result0, float addrspace(1)* %out, align 4
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45 ret void
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46 }
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47
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48 ; SI-LABEL: {{^}}test_div_scale_f64_1:
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49 ; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
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50 ; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
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51 ; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]
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52 ; SI: buffer_store_dwordx2 [[RESULT0]]
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53 ; SI: s_endpgm
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54 define amdgpu_kernel void @test_div_scale_f64_1(double addrspace(1)* %out, double addrspace(1)* %aptr, double addrspace(1)* %in) nounwind {
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55 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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56 %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
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57 %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
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58
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59 %a = load volatile double, double addrspace(1)* %gep.0, align 8
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60 %b = load volatile double, double addrspace(1)* %gep.1, align 8
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61
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62 %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 false) nounwind readnone
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63 %result0 = extractvalue { double, i1 } %result, 0
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64 store double %result0, double addrspace(1)* %out, align 8
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65 ret void
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66 }
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67
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68 ; SI-LABEL: {{^}}test_div_scale_f64_2:
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69 ; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
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70 ; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
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71 ; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]
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72 ; SI: buffer_store_dwordx2 [[RESULT0]]
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73 ; SI: s_endpgm
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74 define amdgpu_kernel void @test_div_scale_f64_2(double addrspace(1)* %out, double addrspace(1)* %aptr, double addrspace(1)* %in) nounwind {
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75 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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76 %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
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77 %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
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78
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79 %a = load volatile double, double addrspace(1)* %gep.0, align 8
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80 %b = load volatile double, double addrspace(1)* %gep.1, align 8
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81
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82 %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 true) nounwind readnone
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83 %result0 = extractvalue { double, i1 } %result, 0
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84 store double %result0, double addrspace(1)* %out, align 8
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85 ret void
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86 }
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87
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88 ; SI-LABEL: {{^}}test_div_scale_f32_scalar_num_1:
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89 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]]
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90 ; SI-DAG: s_load_dword [[A:s[0-9]+]]
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91 ; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]
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92 ; SI: buffer_store_dword [[RESULT0]]
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93 ; SI: s_endpgm
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94 define amdgpu_kernel void @test_div_scale_f32_scalar_num_1(float addrspace(1)* %out, float addrspace(1)* %in, float %a) nounwind {
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95 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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96 %gep = getelementptr float, float addrspace(1)* %in, i32 %tid
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97
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98 %b = load float, float addrspace(1)* %gep, align 4
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99
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100 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 false) nounwind readnone
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101 %result0 = extractvalue { float, i1 } %result, 0
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102 store float %result0, float addrspace(1)* %out, align 4
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103 ret void
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104 }
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105
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106 ; SI-LABEL: {{^}}test_div_scale_f32_scalar_num_2:
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107 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]]
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108 ; SI-DAG: s_load_dword [[A:s[0-9]+]]
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109 ; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]
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110 ; SI: buffer_store_dword [[RESULT0]]
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111 ; SI: s_endpgm
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112 define amdgpu_kernel void @test_div_scale_f32_scalar_num_2(float addrspace(1)* %out, float addrspace(1)* %in, float %a) nounwind {
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113 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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114 %gep = getelementptr float, float addrspace(1)* %in, i32 %tid
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115
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116 %b = load float, float addrspace(1)* %gep, align 4
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117
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118 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 true) nounwind readnone
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119 %result0 = extractvalue { float, i1 } %result, 0
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120 store float %result0, float addrspace(1)* %out, align 4
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121 ret void
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122 }
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123
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124 ; SI-LABEL: {{^}}test_div_scale_f32_scalar_den_1:
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125 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]]
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126 ; SI-DAG: s_load_dword [[B:s[0-9]+]]
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127 ; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]
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128 ; SI: buffer_store_dword [[RESULT0]]
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129 ; SI: s_endpgm
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130 define amdgpu_kernel void @test_div_scale_f32_scalar_den_1(float addrspace(1)* %out, float addrspace(1)* %in, float %b) nounwind {
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131 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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132 %gep = getelementptr float, float addrspace(1)* %in, i32 %tid
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133
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134 %a = load float, float addrspace(1)* %gep, align 4
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135
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136 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 false) nounwind readnone
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137 %result0 = extractvalue { float, i1 } %result, 0
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138 store float %result0, float addrspace(1)* %out, align 4
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139 ret void
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140 }
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141
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142 ; SI-LABEL: {{^}}test_div_scale_f32_scalar_den_2:
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143 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]]
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144 ; SI-DAG: s_load_dword [[B:s[0-9]+]]
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145 ; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]
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146 ; SI: buffer_store_dword [[RESULT0]]
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147 ; SI: s_endpgm
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148 define amdgpu_kernel void @test_div_scale_f32_scalar_den_2(float addrspace(1)* %out, float addrspace(1)* %in, float %b) nounwind {
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149 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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150 %gep = getelementptr float, float addrspace(1)* %in, i32 %tid
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151
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152 %a = load float, float addrspace(1)* %gep, align 4
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153
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154 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 true) nounwind readnone
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155 %result0 = extractvalue { float, i1 } %result, 0
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156 store float %result0, float addrspace(1)* %out, align 4
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157 ret void
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158 }
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159
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160 ; SI-LABEL: {{^}}test_div_scale_f64_scalar_num_1:
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161 ; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]]
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162 ; SI-DAG: s_load_dwordx2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd
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163 ; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]
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164 ; SI: buffer_store_dwordx2 [[RESULT0]]
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165 ; SI: s_endpgm
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166 define amdgpu_kernel void @test_div_scale_f64_scalar_num_1(double addrspace(1)* %out, double addrspace(1)* %in, double %a) nounwind {
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167 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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168 %gep = getelementptr double, double addrspace(1)* %in, i32 %tid
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169
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170 %b = load double, double addrspace(1)* %gep, align 8
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171
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172 %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 false) nounwind readnone
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173 %result0 = extractvalue { double, i1 } %result, 0
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174 store double %result0, double addrspace(1)* %out, align 8
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175 ret void
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176 }
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177
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178 ; SI-LABEL: {{^}}test_div_scale_f64_scalar_num_2:
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179 ; SI-DAG: s_load_dwordx2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd
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180 ; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]]
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181 ; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]
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182 ; SI: buffer_store_dwordx2 [[RESULT0]]
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183 ; SI: s_endpgm
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184 define amdgpu_kernel void @test_div_scale_f64_scalar_num_2(double addrspace(1)* %out, double addrspace(1)* %in, double %a) nounwind {
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185 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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186 %gep = getelementptr double, double addrspace(1)* %in, i32 %tid
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187
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188 %b = load double, double addrspace(1)* %gep, align 8
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189
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190 %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 true) nounwind readnone
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191 %result0 = extractvalue { double, i1 } %result, 0
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192 store double %result0, double addrspace(1)* %out, align 8
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193 ret void
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194 }
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195
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196 ; SI-LABEL: {{^}}test_div_scale_f64_scalar_den_1:
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197 ; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]]
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198 ; SI-DAG: s_load_dwordx2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd
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199 ; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[A]]
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200 ; SI: buffer_store_dwordx2 [[RESULT0]]
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201 ; SI: s_endpgm
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202 define amdgpu_kernel void @test_div_scale_f64_scalar_den_1(double addrspace(1)* %out, double addrspace(1)* %in, double %b) nounwind {
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203 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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204 %gep = getelementptr double, double addrspace(1)* %in, i32 %tid
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205
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206 %a = load double, double addrspace(1)* %gep, align 8
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207
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208 %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 false) nounwind readnone
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209 %result0 = extractvalue { double, i1 } %result, 0
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210 store double %result0, double addrspace(1)* %out, align 8
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211 ret void
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212 }
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213
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214 ; SI-LABEL: {{^}}test_div_scale_f64_scalar_den_2:
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215 ; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]]
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216 ; SI-DAG: s_load_dwordx2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xd
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217 ; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[A]]
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218 ; SI: buffer_store_dwordx2 [[RESULT0]]
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219 ; SI: s_endpgm
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220 define amdgpu_kernel void @test_div_scale_f64_scalar_den_2(double addrspace(1)* %out, double addrspace(1)* %in, double %b) nounwind {
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221 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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222 %gep = getelementptr double, double addrspace(1)* %in, i32 %tid
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223
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224 %a = load double, double addrspace(1)* %gep, align 8
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225
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226 %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 true) nounwind readnone
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227 %result0 = extractvalue { double, i1 } %result, 0
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228 store double %result0, double addrspace(1)* %out, align 8
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229 ret void
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230 }
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231
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232 ; SI-LABEL: {{^}}test_div_scale_f32_all_scalar_1:
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233 ; SI-DAG: s_load_dword [[A:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0x13
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234 ; SI-DAG: s_load_dword [[B:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0x1c
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235 ; SI: v_mov_b32_e32 [[VA:v[0-9]+]], [[A]]
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236 ; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[VA]]
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237 ; SI: buffer_store_dword [[RESULT0]]
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238 ; SI: s_endpgm
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239 define amdgpu_kernel void @test_div_scale_f32_all_scalar_1(float addrspace(1)* %out, [8 x i32], float %a, [8 x i32], float %b) nounwind {
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240 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 false) nounwind readnone
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241 %result0 = extractvalue { float, i1 } %result, 0
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242 store float %result0, float addrspace(1)* %out, align 4
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243 ret void
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244 }
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245
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246 ; SI-LABEL: {{^}}test_div_scale_f32_all_scalar_2:
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247 ; SI-DAG: s_load_dword [[A:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0x13
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248 ; SI-DAG: s_load_dword [[B:s[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 0x1c
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249 ; SI: v_mov_b32_e32 [[VB:v[0-9]+]], [[B]]
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250 ; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[VB]], [[A]]
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251 ; SI: buffer_store_dword [[RESULT0]]
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252 ; SI: s_endpgm
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253 define amdgpu_kernel void @test_div_scale_f32_all_scalar_2(float addrspace(1)* %out, [8 x i32], float %a, [8 x i32], float %b) nounwind {
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254 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 true) nounwind readnone
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255 %result0 = extractvalue { float, i1 } %result, 0
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256 store float %result0, float addrspace(1)* %out, align 4
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257 ret void
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258 }
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259
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260 ; SI-LABEL: {{^}}test_div_scale_f64_all_scalar_1:
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261 ; SI-DAG: s_load_dwordx2 s{{\[}}[[A_LO:[0-9]+]]:[[A_HI:[0-9]+]]{{\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x13
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262 ; SI-DAG: s_load_dwordx2 [[B:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x1d
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263 ; SI-DAG: v_mov_b32_e32 v[[VA_LO:[0-9]+]], s[[A_LO]]
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264 ; SI-DAG: v_mov_b32_e32 v[[VA_HI:[0-9]+]], s[[A_HI]]
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265 ; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], v{{\[}}[[VA_LO]]:[[VA_HI]]{{\]}}
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266 ; SI: buffer_store_dwordx2 [[RESULT0]]
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267 ; SI: s_endpgm
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268 define amdgpu_kernel void @test_div_scale_f64_all_scalar_1(double addrspace(1)* %out, [8 x i32], double %a, [8 x i32], double %b) nounwind {
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269 %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 false) nounwind readnone
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270 %result0 = extractvalue { double, i1 } %result, 0
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271 store double %result0, double addrspace(1)* %out, align 8
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272 ret void
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273 }
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274
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275 ; SI-LABEL: {{^}}test_div_scale_f64_all_scalar_2:
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276 ; SI-DAG: s_load_dwordx2 [[A:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0x13
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277 ; SI-DAG: s_load_dwordx2 s{{\[}}[[B_LO:[0-9]+]]:[[B_HI:[0-9]+]]{{\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x1d
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278 ; SI-DAG: v_mov_b32_e32 v[[VB_LO:[0-9]+]], s[[B_LO]]
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279 ; SI-DAG: v_mov_b32_e32 v[[VB_HI:[0-9]+]], s[[B_HI]]
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280 ; SI: v_div_scale_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], v{{\[}}[[VB_LO]]:[[VB_HI]]{{\]}}, [[A]]
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281 ; SI: buffer_store_dwordx2 [[RESULT0]]
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282 ; SI: s_endpgm
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283 define amdgpu_kernel void @test_div_scale_f64_all_scalar_2(double addrspace(1)* %out, [8 x i32], double %a, [8 x i32], double %b) nounwind {
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284 %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 true) nounwind readnone
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285 %result0 = extractvalue { double, i1 } %result, 0
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286 store double %result0, double addrspace(1)* %out, align 8
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287 ret void
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288 }
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289
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290 ; SI-LABEL: {{^}}test_div_scale_f32_inline_imm_num:
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291 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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292 ; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[A]], [[A]], 1.0
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293 ; SI: buffer_store_dword [[RESULT0]]
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294 ; SI: s_endpgm
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295 define amdgpu_kernel void @test_div_scale_f32_inline_imm_num(float addrspace(1)* %out, float addrspace(1)* %in) nounwind {
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296 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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297 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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298 %a = load float, float addrspace(1)* %gep.0, align 4
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299
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300 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float 1.0, float %a, i1 false) nounwind readnone
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301 %result0 = extractvalue { float, i1 } %result, 0
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302 store float %result0, float addrspace(1)* %out, align 4
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303 ret void
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304 }
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305
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306 ; SI-LABEL: {{^}}test_div_scale_f32_inline_imm_den:
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307 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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308 ; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], 2.0, 2.0, [[A]]
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309 ; SI: buffer_store_dword [[RESULT0]]
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310 ; SI: s_endpgm
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311 define amdgpu_kernel void @test_div_scale_f32_inline_imm_den(float addrspace(1)* %out, float addrspace(1)* %in) nounwind {
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312 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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313 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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314 %a = load float, float addrspace(1)* %gep.0, align 4
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315
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316 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float 2.0, i1 false) nounwind readnone
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317 %result0 = extractvalue { float, i1 } %result, 0
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318 store float %result0, float addrspace(1)* %out, align 4
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319 ret void
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320 }
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321
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221
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322 ; SI-LABEL: {{^}}test_div_scale_f32_fneg_num:
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323 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
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324 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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325 ; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], -[[A]]
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326 ; SI: buffer_store_dword [[RESULT0]]
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327 ; SI: s_endpgm
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328 define amdgpu_kernel void @test_div_scale_f32_fneg_num(float addrspace(1)* %out, float addrspace(1)* %in) nounwind {
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329 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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330 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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331 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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332
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333 %a = load volatile float, float addrspace(1)* %gep.0, align 4
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334 %b = load volatile float, float addrspace(1)* %gep.1, align 4
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335
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336 %a.fneg = fneg float %a
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337
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338 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a.fneg, float %b, i1 false) nounwind readnone
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339 %result0 = extractvalue { float, i1 } %result, 0
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340 store float %result0, float addrspace(1)* %out, align 4
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341 ret void
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342 }
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343
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150
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344 ; SI-LABEL: {{^}}test_div_scale_f32_fabs_num:
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345 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
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346 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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347 ; SI: v_and_b32_e32 [[ABS_A:v[0-9]+]], 0x7fffffff, [[A]]
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348 ; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[B]], [[B]], [[ABS_A]]
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349 ; SI: buffer_store_dword [[RESULT0]]
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350 ; SI: s_endpgm
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351 define amdgpu_kernel void @test_div_scale_f32_fabs_num(float addrspace(1)* %out, float addrspace(1)* %in) nounwind {
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352 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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353 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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354 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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355
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356 %a = load volatile float, float addrspace(1)* %gep.0, align 4
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357 %b = load volatile float, float addrspace(1)* %gep.1, align 4
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358
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359 %a.fabs = call float @llvm.fabs.f32(float %a) nounwind readnone
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360
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361 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a.fabs, float %b, i1 false) nounwind readnone
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362 %result0 = extractvalue { float, i1 } %result, 0
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363 store float %result0, float addrspace(1)* %out, align 4
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364 ret void
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365 }
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366
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221
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367 ; SI-LABEL: {{^}}test_div_scale_f32_fneg_den:
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368 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
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369 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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370 ; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], -[[B]], -[[B]], [[A]]
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371 ; SI: buffer_store_dword [[RESULT0]]
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372 ; SI: s_endpgm
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373 define amdgpu_kernel void @test_div_scale_f32_fneg_den(float addrspace(1)* %out, float addrspace(1)* %in) nounwind {
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374 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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375 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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376 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
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377
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378 %a = load volatile float, float addrspace(1)* %gep.0, align 4
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379 %b = load volatile float, float addrspace(1)* %gep.1, align 4
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380
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381 %b.fneg = fneg float %b
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382
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383 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b.fneg, i1 false) nounwind readnone
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384 %result0 = extractvalue { float, i1 } %result, 0
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385 store float %result0, float addrspace(1)* %out, align 4
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386 ret void
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|
|
387 }
|
|
|
388
|
|
150
|
389 ; SI-LABEL: {{^}}test_div_scale_f32_fabs_den:
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|
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390 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64
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|
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391 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
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392 ; SI: v_and_b32_e32 [[ABS_B:v[0-9]+]], 0x7fffffff, [[B]]
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393 ; SI: v_div_scale_f32 [[RESULT0:v[0-9]+]], [[RESULT1:s\[[0-9]+:[0-9]+\]]], [[ABS_B]], [[ABS_B]], [[A]]
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394 ; SI: buffer_store_dword [[RESULT0]]
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395 ; SI: s_endpgm
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|
396 define amdgpu_kernel void @test_div_scale_f32_fabs_den(float addrspace(1)* %out, float addrspace(1)* %in) nounwind {
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397 %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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398 %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
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399 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
|
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400
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401 %a = load volatile float, float addrspace(1)* %gep.0, align 4
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402 %b = load volatile float, float addrspace(1)* %gep.1, align 4
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403
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404 %b.fabs = call float @llvm.fabs.f32(float %b) nounwind readnone
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405
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406 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b.fabs, i1 false) nounwind readnone
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407 %result0 = extractvalue { float, i1 } %result, 0
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|
|
408 store float %result0, float addrspace(1)* %out, align 4
|
|
|
409 ret void
|
|
|
410 }
|
|
|
411
|
|
|
412 ; SI-LABEL: {{^}}test_div_scale_f32_val_undef_val:
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|
|
413 ; SI: s_mov_b32 [[K:s[0-9]+]], 0x41000000
|
|
|
414 ; SI: v_div_scale_f32 v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, [[K]], v{{[0-9]+}}, [[K]]
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|
|
415 define amdgpu_kernel void @test_div_scale_f32_val_undef_val(float addrspace(1)* %out) #0 {
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416 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float 8.0, float undef, i1 false)
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|
|
417 %result0 = extractvalue { float, i1 } %result, 0
|
|
|
418 store float %result0, float addrspace(1)* %out, align 4
|
|
|
419 ret void
|
|
|
420 }
|
|
|
421
|
|
|
422 ; SI-LABEL: {{^}}test_div_scale_f32_undef_val_val:
|
|
|
423 ; SI: s_mov_b32 [[K:s[0-9]+]], 0x41000000
|
|
|
424 ; SI: v_div_scale_f32 v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, [[K]], [[K]], v{{[0-9]+}}
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|
425 define amdgpu_kernel void @test_div_scale_f32_undef_val_val(float addrspace(1)* %out) #0 {
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|
426 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float undef, float 8.0, i1 false)
|
|
|
427 %result0 = extractvalue { float, i1 } %result, 0
|
|
|
428 store float %result0, float addrspace(1)* %out, align 4
|
|
|
429 ret void
|
|
|
430 }
|
|
|
431
|
|
|
432 ; SI-LABEL: {{^}}test_div_scale_f32_undef_undef_val:
|
|
|
433 ; SI-NOT: v0
|
|
|
434 ; SI: v_div_scale_f32 v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, s0, s0, v0
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|
435 define amdgpu_kernel void @test_div_scale_f32_undef_undef_val(float addrspace(1)* %out) #0 {
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|
|
436 %result = call { float, i1 } @llvm.amdgcn.div.scale.f32(float undef, float undef, i1 false)
|
|
|
437 %result0 = extractvalue { float, i1 } %result, 0
|
|
|
438 store float %result0, float addrspace(1)* %out, align 4
|
|
|
439 ret void
|
|
|
440 }
|
|
|
441
|
|
|
442 ; SI-LABEL: {{^}}test_div_scale_f64_val_undef_val:
|
|
|
443 ; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0{{$}}
|
|
|
444 ; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0x40200000
|
|
|
445 ; SI: v_div_scale_f64 v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}, v[0:1], s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}
|
|
|
446 define amdgpu_kernel void @test_div_scale_f64_val_undef_val(double addrspace(1)* %out) #0 {
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|
|
447 %result = call { double, i1 } @llvm.amdgcn.div.scale.f64(double 8.0, double undef, i1 false)
|
|
|
448 %result0 = extractvalue { double, i1 } %result, 0
|
|
|
449 store double %result0, double addrspace(1)* %out, align 8
|
|
|
450 ret void
|
|
|
451 }
|
|
|
452
|
|
|
453 attributes #0 = { nounwind }
|
|
|
454 attributes #1 = { nounwind readnone speculatable }
|
