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221
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1 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,SI %s
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2 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,VI,GFX89 %s
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3 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX89,GFX9 %s
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150
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4
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5 declare half @llvm.rint.f16(half %a)
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6 declare <2 x half> @llvm.rint.v2f16(<2 x half> %a)
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7
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8 ; GCN-LABEL: {{^}}rint_f16
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9 ; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
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10 ; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
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11 ; SI: v_rndne_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]]
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12 ; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
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13 ; GFX89: v_rndne_f16_e32 v[[R_F16:[0-9]+]], v[[A_F16]]
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14 ; GCN: buffer_store_short v[[R_F16]]
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15 ; GCN: s_endpgm
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16 define amdgpu_kernel void @rint_f16(
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17 half addrspace(1)* %r,
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18 half addrspace(1)* %a) {
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19 entry:
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20 %a.val = load half, half addrspace(1)* %a
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21 %r.val = call half @llvm.rint.f16(half %a.val)
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22 store half %r.val, half addrspace(1)* %r
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23 ret void
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24 }
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25
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26 ; GCN-LABEL: {{^}}rint_v2f16
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27 ; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]]
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28 ; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]]
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29 ; SI-DAG: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
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30 ; SI-DAG: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]]
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31 ; SI-DAG: v_rndne_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]]
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32 ; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]]
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33 ; SI-DAG: v_rndne_f32_e32 v[[R_F32_1:[0-9]+]], v[[A_F32_1]]
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34 ; SI-DAG: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]]
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35 ; SI-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]]
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36 ; SI-NOT: v_and_b32
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37 ; SI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_HI]]
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38
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39 ; VI-DAG: v_rndne_f16_e32 v[[R_F16_0:[0-9]+]], v[[A_V2_F16]]
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40 ; VI-DAG: v_rndne_f16_sdwa v[[R_F16_1:[0-9]+]], v[[A_V2_F16]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1
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41 ; VI-NOT: v_and_b32
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42 ; VI: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_1]]
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43
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44 ; GFX9: v_rndne_f16_e32 v[[R_F16_0:[0-9]+]], v[[A_V2_F16]]
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45 ; GFX9: v_rndne_f16_sdwa v[[R_F16_1:[0-9]+]], v[[A_V2_F16]] dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
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221
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46 ; GFX9: v_pack_b32_f16 v[[R_V2_F16:[0-9]+]], v[[R_F16_0]], v[[R_F16_1]]
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150
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47
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48 ; GCN: buffer_store_dword v[[R_V2_F16]]
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49 ; GCN: s_endpgm
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50
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51 define amdgpu_kernel void @rint_v2f16(
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52 <2 x half> addrspace(1)* %r,
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53 <2 x half> addrspace(1)* %a) {
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54 entry:
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55 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
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56 %r.val = call <2 x half> @llvm.rint.v2f16(<2 x half> %a.val)
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57 store <2 x half> %r.val, <2 x half> addrspace(1)* %r
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58 ret void
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59 }
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