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150
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1 ; RUN: llc -march=amdgcn -amdgpu-atomic-optimizations=false -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI,SICIVI,FUNC %s
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2 ; RUN: llc -march=amdgcn -mcpu=bonaire -amdgpu-atomic-optimizations=false -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,FUNC %s
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3 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-atomic-optimizations=false -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI,SICIVI,FUNC %s
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4 ; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-atomic-optimizations=false -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,FUNC %s
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5 ; RUN: llc -march=r600 -mcpu=redwood -amdgpu-atomic-optimizations=false -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=EG,FUNC %s
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6
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7 ; FUNC-LABEL: {{^}}lds_atomic_xchg_ret_i32:
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8 ; EG: LDS_WRXCHG_RET *
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9
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10 ; SICIVI-DAG: s_mov_b32 m0
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11 ; GFX9-NOT: m0
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12
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13 ; GCN-DAG: s_load_dword [[SPTR:s[0-9]+]],
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14 ; GCN-DAG: v_mov_b32_e32 [[DATA:v[0-9]+]], 4
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15 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
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16 ; GCN: ds_wrxchg_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]]
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17 ; GCN: buffer_store_dword [[RESULT]],
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18 ; GCN: s_endpgm
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19 define amdgpu_kernel void @lds_atomic_xchg_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
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20 %result = atomicrmw xchg i32 addrspace(3)* %ptr, i32 4 seq_cst
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21 store i32 %result, i32 addrspace(1)* %out, align 4
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22 ret void
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23 }
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24
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25 ; FUNC-LABEL: {{^}}lds_atomic_xchg_ret_i32_offset:
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26 ; SICIVI: s_mov_b32 m0
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27 ; GFX9-NOT: m0
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28
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29 ; EG: LDS_WRXCHG_RET *
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30 ; GCN: ds_wrxchg_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
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31 ; GCN: s_endpgm
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32 define amdgpu_kernel void @lds_atomic_xchg_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
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33 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
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34 %result = atomicrmw xchg i32 addrspace(3)* %gep, i32 4 seq_cst
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35 store i32 %result, i32 addrspace(1)* %out, align 4
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36 ret void
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37 }
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38
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39 ; FUNC-LABEL: {{^}}lds_atomic_xchg_ret_f32_offset:
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40 ; SICIVI: s_mov_b32 m0
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41 ; GFX9-NOT: m0
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42
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43 ; EG: LDS_WRXCHG_RET *
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44 ; GCN: ds_wrxchg_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
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45 ; GCN: s_endpgm
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46 define amdgpu_kernel void @lds_atomic_xchg_ret_f32_offset(float addrspace(1)* %out, float addrspace(3)* %ptr) nounwind {
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47 %gep = getelementptr float, float addrspace(3)* %ptr, i32 4
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48 %result = atomicrmw xchg float addrspace(3)* %gep, float 4.0 seq_cst
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49 store float %result, float addrspace(1)* %out, align 4
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50 ret void
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51 }
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52
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53 ; XXX - Is it really necessary to load 4 into VGPR?
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54 ; FUNC-LABEL: {{^}}lds_atomic_add_ret_i32:
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55 ; EG: LDS_ADD_RET *
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56
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57 ; SICIVI-DAG: s_mov_b32 m0
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58 ; GFX9-NOT: m0
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59
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60 ; GCN-DAG: s_load_dword [[SPTR:s[0-9]+]],
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61 ; GCN-DAG: v_mov_b32_e32 [[DATA:v[0-9]+]], 4
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62 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
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63 ; GCN: ds_add_rtn_u32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]]
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64 ; GCN: buffer_store_dword [[RESULT]],
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65 ; GCN: s_endpgm
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66 define amdgpu_kernel void @lds_atomic_add_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
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67 %result = atomicrmw add i32 addrspace(3)* %ptr, i32 4 seq_cst
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68 store i32 %result, i32 addrspace(1)* %out, align 4
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69 ret void
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70 }
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71
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72 ; FUNC-LABEL: {{^}}lds_atomic_add_ret_i32_offset:
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73 ; SICIVI: s_mov_b32 m0
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74 ; GFX9-NOT: m0
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75
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76 ; EG: LDS_ADD_RET *
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77 ; GCN: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
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78 ; GCN: s_endpgm
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79 define amdgpu_kernel void @lds_atomic_add_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
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80 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
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81 %result = atomicrmw add i32 addrspace(3)* %gep, i32 4 seq_cst
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82 store i32 %result, i32 addrspace(1)* %out, align 4
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83 ret void
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84 }
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85
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86 ; FUNC-LABEL: {{^}}lds_atomic_add_ret_i32_bad_si_offset:
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87 ; SICIVI: s_mov_b32 m0
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88 ; GFX9-NOT: m0
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89
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90 ; EG: LDS_ADD_RET *
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91 ; SI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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92 ; CIVI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
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93 ; GCN: s_endpgm
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94 define amdgpu_kernel void @lds_atomic_add_ret_i32_bad_si_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr, i32 %a, i32 %b) nounwind {
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95 %sub = sub i32 %a, %b
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96 %add = add i32 %sub, 4
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97 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 %add
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98 %result = atomicrmw add i32 addrspace(3)* %gep, i32 4 seq_cst
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99 store i32 %result, i32 addrspace(1)* %out, align 4
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100 ret void
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101 }
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102
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103 ; FUNC-LABEL: {{^}}lds_atomic_add1_ret_i32:
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104 ; EG: LDS_ADD_RET *
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105
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106 ; SICIVI-DAG: s_mov_b32 m0
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107 ; GFX9-NOT: m0
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108
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109 ; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1{{$}}
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110 ; GCN: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[ONE]]
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111 ; GCN: s_endpgm
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112 define amdgpu_kernel void @lds_atomic_add1_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
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113 %result = atomicrmw add i32 addrspace(3)* %ptr, i32 1 seq_cst
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114 store i32 %result, i32 addrspace(1)* %out, align 4
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115 ret void
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116 }
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117
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118 ; FUNC-LABEL: {{^}}lds_atomic_add1_ret_i32_offset:
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119 ; EG: LDS_ADD_RET *
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120
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121 ; SICIVI-DAG: s_mov_b32 m0
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122 ; GFX9-NOT: m0
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123
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124 ; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1{{$}}
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125 ; GCN: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[ONE]] offset:16
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126 ; GCN: s_endpgm
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127 define amdgpu_kernel void @lds_atomic_add1_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
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128 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
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129 %result = atomicrmw add i32 addrspace(3)* %gep, i32 1 seq_cst
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130 store i32 %result, i32 addrspace(1)* %out, align 4
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131 ret void
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132 }
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133
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134 ; FUNC-LABEL: {{^}}lds_atomic_add1_ret_i32_bad_si_offset:
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135 ; SICIVI: s_mov_b32 m0
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136 ; GFX9-NOT: m0
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137
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138 ; EG: LDS_ADD_RET *
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139 ; SI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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140 ; CIVI: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
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141 ; GCN: s_endpgm
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142 define amdgpu_kernel void @lds_atomic_add1_ret_i32_bad_si_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr, i32 %a, i32 %b) nounwind {
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143 %sub = sub i32 %a, %b
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144 %add = add i32 %sub, 4
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145 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 %add
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146 %result = atomicrmw add i32 addrspace(3)* %gep, i32 1 seq_cst
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147 store i32 %result, i32 addrspace(1)* %out, align 4
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148 ret void
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149 }
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150
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151 ; FUNC-LABEL: {{^}}lds_atomic_sub_ret_i32:
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152 ; EG: LDS_SUB_RET *
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153
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154 ; SICIVI: s_mov_b32 m0
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155 ; GFX9-NOT: m0
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156
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157 ; GCN: ds_sub_rtn_u32
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158 ; GCN: s_endpgm
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159 define amdgpu_kernel void @lds_atomic_sub_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
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160 %result = atomicrmw sub i32 addrspace(3)* %ptr, i32 4 seq_cst
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161 store i32 %result, i32 addrspace(1)* %out, align 4
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162 ret void
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163 }
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164
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165 ; FUNC-LABEL: {{^}}lds_atomic_sub_ret_i32_offset:
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166 ; EG: LDS_SUB_RET *
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167
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168 ; SICIVI: s_mov_b32 m0
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169 ; GFX9-NOT: m0
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170
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171 ; GCN: ds_sub_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
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172 ; GCN: s_endpgm
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173 define amdgpu_kernel void @lds_atomic_sub_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
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174 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
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175 %result = atomicrmw sub i32 addrspace(3)* %gep, i32 4 seq_cst
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176 store i32 %result, i32 addrspace(1)* %out, align 4
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177 ret void
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178 }
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179
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180 ; FUNC-LABEL: {{^}}lds_atomic_sub1_ret_i32:
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181 ; EG: LDS_SUB_RET *
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182
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183 ; SICIVI-DAG: s_mov_b32 m0
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184 ; GFX9-NOT: m0
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185
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186 ; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1{{$}}
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187 ; GCN: ds_sub_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[ONE]]
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188 ; GCN: s_endpgm
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189 define amdgpu_kernel void @lds_atomic_sub1_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
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190 %result = atomicrmw sub i32 addrspace(3)* %ptr, i32 1 seq_cst
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191 store i32 %result, i32 addrspace(1)* %out, align 4
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192 ret void
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193 }
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194
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195 ; FUNC-LABEL: {{^}}lds_atomic_sub1_ret_i32_offset:
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196 ; EG: LDS_SUB_RET *
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197
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198 ; SICIVI-DAG: s_mov_b32 m0
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199 ; GFX9-NOT: m0
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200
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201 ; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1{{$}}
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202 ; GCN: ds_sub_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[ONE]] offset:16
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203 ; GCN: s_endpgm
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204 define amdgpu_kernel void @lds_atomic_sub1_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
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205 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
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206 %result = atomicrmw sub i32 addrspace(3)* %gep, i32 1 seq_cst
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207 store i32 %result, i32 addrspace(1)* %out, align 4
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208 ret void
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209 }
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210
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211 ; FUNC-LABEL: {{^}}lds_atomic_and_ret_i32:
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212 ; EG: LDS_AND_RET *
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213
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214 ; SICIVI-DAG: s_mov_b32 m0
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215 ; GFX9-NOT: m0
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216
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217 ; GCN: ds_and_rtn_b32
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218 ; GCN: s_endpgm
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219 define amdgpu_kernel void @lds_atomic_and_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
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220 %result = atomicrmw and i32 addrspace(3)* %ptr, i32 4 seq_cst
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221 store i32 %result, i32 addrspace(1)* %out, align 4
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222 ret void
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223 }
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224
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225 ; FUNC-LABEL: {{^}}lds_atomic_and_ret_i32_offset:
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226 ; SICIVI: s_mov_b32 m0
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227 ; GFX9-NOT: m0
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228
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229 ; EG: LDS_AND_RET *
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230 ; GCN: ds_and_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
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231 ; GCN: s_endpgm
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232 define amdgpu_kernel void @lds_atomic_and_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
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233 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
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234 %result = atomicrmw and i32 addrspace(3)* %gep, i32 4 seq_cst
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235 store i32 %result, i32 addrspace(1)* %out, align 4
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236 ret void
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237 }
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238
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239 ; FUNC-LABEL: {{^}}lds_atomic_or_ret_i32:
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240 ; SICIVI: s_mov_b32 m0
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241 ; GFX9-NOT: m0
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242
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243 ; EG: LDS_OR_RET *
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244 ; GCN: ds_or_rtn_b32
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245 ; GCN: s_endpgm
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246 define amdgpu_kernel void @lds_atomic_or_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
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247 %result = atomicrmw or i32 addrspace(3)* %ptr, i32 4 seq_cst
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248 store i32 %result, i32 addrspace(1)* %out, align 4
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249 ret void
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250 }
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251
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252 ; FUNC-LABEL: {{^}}lds_atomic_or_ret_i32_offset:
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253 ; SICIVI: s_mov_b32 m0
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254 ; GFX9-NOT: m0
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255
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256 ; EG: LDS_OR_RET *
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257 ; GCN: ds_or_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
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258 ; GCN: s_endpgm
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259 define amdgpu_kernel void @lds_atomic_or_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
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260 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
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261 %result = atomicrmw or i32 addrspace(3)* %gep, i32 4 seq_cst
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262 store i32 %result, i32 addrspace(1)* %out, align 4
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263 ret void
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264 }
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265
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266 ; FUNC-LABEL: {{^}}lds_atomic_xor_ret_i32:
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267 ; SICIVI: s_mov_b32 m0
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268 ; GFX9-NOT: m0
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269
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270 ; EG: LDS_XOR_RET *
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271 ; GCN: ds_xor_rtn_b32
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272 ; GCN: s_endpgm
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273 define amdgpu_kernel void @lds_atomic_xor_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
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274 %result = atomicrmw xor i32 addrspace(3)* %ptr, i32 4 seq_cst
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275 store i32 %result, i32 addrspace(1)* %out, align 4
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276 ret void
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277 }
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278
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279 ; FUNC-LABEL: {{^}}lds_atomic_xor_ret_i32_offset:
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280 ; SICIVI: s_mov_b32 m0
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281 ; GFX9-NOT: m0
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282
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283 ; EG: LDS_XOR_RET *
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284 ; GCN: ds_xor_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
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285 ; GCN: s_endpgm
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286 define amdgpu_kernel void @lds_atomic_xor_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
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287 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
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288 %result = atomicrmw xor i32 addrspace(3)* %gep, i32 4 seq_cst
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289 store i32 %result, i32 addrspace(1)* %out, align 4
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290 ret void
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291 }
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292
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293 ; FIXME: There is no atomic nand instr
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294 ; XFUNC-LABEL: {{^}}lds_atomic_nand_ret_i32:uction, so we somehow need to expand this.
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295 ; define amdgpu_kernel void @lds_atomic_nand_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
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296 ; %result = atomicrmw nand i32 addrspace(3)* %ptr, i32 4 seq_cst
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297 ; store i32 %result, i32 addrspace(1)* %out, align 4
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298 ; ret void
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299 ; }
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300
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301 ; FUNC-LABEL: {{^}}lds_atomic_min_ret_i32:
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302 ; SICIVI: s_mov_b32 m0
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303 ; GFX9-NOT: m0
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304
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305 ; EG: LDS_MIN_INT_RET *
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306 ; GCN: ds_min_rtn_i32
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307 ; GCN: s_endpgm
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308 define amdgpu_kernel void @lds_atomic_min_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
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309 %result = atomicrmw min i32 addrspace(3)* %ptr, i32 4 seq_cst
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310 store i32 %result, i32 addrspace(1)* %out, align 4
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311 ret void
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312 }
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313
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314 ; FUNC-LABEL: {{^}}lds_atomic_min_ret_i32_offset:
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315 ; SICIVI: s_mov_b32 m0
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316 ; GFX9-NOT: m0
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317
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318 ; EG: LDS_MIN_INT_RET *
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319 ; GCN: ds_min_rtn_i32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
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320 ; GCN: s_endpgm
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321 define amdgpu_kernel void @lds_atomic_min_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
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322 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
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323 %result = atomicrmw min i32 addrspace(3)* %gep, i32 4 seq_cst
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324 store i32 %result, i32 addrspace(1)* %out, align 4
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325 ret void
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326 }
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327
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328 ; FUNC-LABEL: {{^}}lds_atomic_max_ret_i32:
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329 ; SICIVI: s_mov_b32 m0
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330 ; GFX9-NOT: m0
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331
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332 ; EG: LDS_MAX_INT_RET *
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333 ; GCN: ds_max_rtn_i32
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334 ; GCN: s_endpgm
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335 define amdgpu_kernel void @lds_atomic_max_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
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336 %result = atomicrmw max i32 addrspace(3)* %ptr, i32 4 seq_cst
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337 store i32 %result, i32 addrspace(1)* %out, align 4
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338 ret void
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339 }
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340
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341 ; FUNC-LABEL: {{^}}lds_atomic_max_ret_i32_offset:
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342 ; SICIVI: s_mov_b32 m0
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343 ; GFX9-NOT: m0
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344
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345 ; EG: LDS_MAX_INT_RET *
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346 ; GCN: ds_max_rtn_i32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
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347 ; GCN: s_endpgm
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348 define amdgpu_kernel void @lds_atomic_max_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
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349 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
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350 %result = atomicrmw max i32 addrspace(3)* %gep, i32 4 seq_cst
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351 store i32 %result, i32 addrspace(1)* %out, align 4
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352 ret void
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353 }
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354
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355 ; FUNC-LABEL: {{^}}lds_atomic_umin_ret_i32:
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356 ; SICIVI: s_mov_b32 m0
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357 ; GFX9-NOT: m0
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358
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359 ; EG: LDS_MIN_UINT_RET *
|
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360 ; GCN: ds_min_rtn_u32
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361 ; GCN: s_endpgm
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362 define amdgpu_kernel void @lds_atomic_umin_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
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363 %result = atomicrmw umin i32 addrspace(3)* %ptr, i32 4 seq_cst
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364 store i32 %result, i32 addrspace(1)* %out, align 4
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365 ret void
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|
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366 }
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367
|
|
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368 ; FUNC-LABEL: {{^}}lds_atomic_umin_ret_i32_offset:
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369 ; SICIVI: s_mov_b32 m0
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370 ; GFX9-NOT: m0
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|
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371
|
|
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372 ; EG: LDS_MIN_UINT_RET *
|
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373 ; GCN: ds_min_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
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374 ; GCN: s_endpgm
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375 define amdgpu_kernel void @lds_atomic_umin_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
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376 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
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377 %result = atomicrmw umin i32 addrspace(3)* %gep, i32 4 seq_cst
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|
|
378 store i32 %result, i32 addrspace(1)* %out, align 4
|
|
|
379 ret void
|
|
|
380 }
|
|
|
381
|
|
|
382 ; FUNC-LABEL: {{^}}lds_atomic_umax_ret_i32:
|
|
|
383 ; SICIVI: s_mov_b32 m0
|
|
|
384 ; GFX9-NOT: m0
|
|
|
385
|
|
|
386 ; EG: LDS_MAX_UINT_RET *
|
|
|
387 ; GCN: ds_max_rtn_u32
|
|
|
388 ; GCN: s_endpgm
|
|
|
389 define amdgpu_kernel void @lds_atomic_umax_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
|
|
|
390 %result = atomicrmw umax i32 addrspace(3)* %ptr, i32 4 seq_cst
|
|
|
391 store i32 %result, i32 addrspace(1)* %out, align 4
|
|
|
392 ret void
|
|
|
393 }
|
|
|
394
|
|
|
395 ; FUNC-LABEL: {{^}}lds_atomic_umax_ret_i32_offset:
|
|
|
396 ; SICIVI: s_mov_b32 m0
|
|
|
397 ; GFX9-NOT: m0
|
|
|
398
|
|
|
399 ; EG: LDS_MAX_UINT_RET *
|
|
|
400 ; GCN: ds_max_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
|
|
|
401 ; GCN: s_endpgm
|
|
|
402 define amdgpu_kernel void @lds_atomic_umax_ret_i32_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) nounwind {
|
|
|
403 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
|
|
|
404 %result = atomicrmw umax i32 addrspace(3)* %gep, i32 4 seq_cst
|
|
|
405 store i32 %result, i32 addrspace(1)* %out, align 4
|
|
|
406 ret void
|
|
|
407 }
|
|
|
408
|
|
|
409 ; FUNC-LABEL: {{^}}lds_atomic_xchg_noret_i32:
|
|
|
410 ; SICIVI-DAG: s_mov_b32 m0
|
|
|
411 ; GFX9-NOT: m0
|
|
|
412
|
|
|
413 ; GCN-DAG: s_load_dword [[SPTR:s[0-9]+]],
|
|
|
414 ; GCN-DAG: v_mov_b32_e32 [[DATA:v[0-9]+]], 4
|
|
|
415 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
|
|
|
416 ; GCN: ds_wrxchg_rtn_b32 [[RESULT:v[0-9]+]], [[VPTR]], [[DATA]]
|
|
|
417 ; GCN: s_endpgm
|
|
|
418 define amdgpu_kernel void @lds_atomic_xchg_noret_i32(i32 addrspace(3)* %ptr) nounwind {
|
|
|
419 %result = atomicrmw xchg i32 addrspace(3)* %ptr, i32 4 seq_cst
|
|
|
420 ret void
|
|
|
421 }
|
|
|
422
|
|
|
423 ; FUNC-LABEL: {{^}}lds_atomic_xchg_noret_i32_offset:
|
|
|
424 ; SICIVI: s_mov_b32 m0
|
|
|
425 ; GFX9-NOT: m0
|
|
|
426
|
|
|
427 ; GCN: ds_wrxchg_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset:16
|
|
|
428 ; GCN: s_endpgm
|
|
|
429 define amdgpu_kernel void @lds_atomic_xchg_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
|
|
|
430 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
|
|
|
431 %result = atomicrmw xchg i32 addrspace(3)* %gep, i32 4 seq_cst
|
|
|
432 ret void
|
|
|
433 }
|
|
|
434
|
|
|
435 ; FUNC-LABEL: {{^}}lds_atomic_add_noret_i32:
|
|
|
436 ; SICIVI-DAG: s_mov_b32 m0
|
|
|
437 ; GFX9-NOT: m0
|
|
|
438
|
|
|
439 ; GCN-DAG: s_load_dword [[SPTR:s[0-9]+]],
|
|
|
440 ; GCN-DAG: v_mov_b32_e32 [[DATA:v[0-9]+]], 4
|
|
|
441 ; GCN-DAG: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
|
|
|
442 ; GCN: ds_add_u32 [[VPTR]], [[DATA]]
|
|
|
443 ; GCN: s_endpgm
|
|
|
444 define amdgpu_kernel void @lds_atomic_add_noret_i32(i32 addrspace(3)* %ptr) nounwind {
|
|
|
445 %result = atomicrmw add i32 addrspace(3)* %ptr, i32 4 seq_cst
|
|
|
446 ret void
|
|
|
447 }
|
|
|
448
|
|
|
449 ; FUNC-LABEL: {{^}}lds_atomic_add_noret_i32_offset:
|
|
|
450 ; SICIVI: s_mov_b32 m0
|
|
|
451 ; GFX9-NOT: m0
|
|
|
452
|
|
|
453 ; GCN: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
|
|
|
454 ; GCN: s_endpgm
|
|
|
455 define amdgpu_kernel void @lds_atomic_add_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
|
|
|
456 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
|
|
|
457 %result = atomicrmw add i32 addrspace(3)* %gep, i32 4 seq_cst
|
|
|
458 ret void
|
|
|
459 }
|
|
|
460
|
|
|
461 ; FUNC-LABEL: {{^}}lds_atomic_add_noret_i32_bad_si_offset
|
|
|
462 ; SICIVI: s_mov_b32 m0
|
|
|
463 ; GFX9-NOT: m0
|
|
|
464
|
|
|
465 ; SI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}}
|
|
|
466 ; CIVI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
|
|
|
467 ; GCN: s_endpgm
|
|
|
468 define amdgpu_kernel void @lds_atomic_add_noret_i32_bad_si_offset(i32 addrspace(3)* %ptr, i32 %a, i32 %b) nounwind {
|
|
|
469 %sub = sub i32 %a, %b
|
|
|
470 %add = add i32 %sub, 4
|
|
|
471 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 %add
|
|
|
472 %result = atomicrmw add i32 addrspace(3)* %gep, i32 4 seq_cst
|
|
|
473 ret void
|
|
|
474 }
|
|
|
475
|
|
|
476 ; FUNC-LABEL: {{^}}lds_atomic_add1_noret_i32:
|
|
|
477 ; SICIVI-DAG: s_mov_b32 m0
|
|
|
478 ; GFX9-NOT: m0
|
|
|
479
|
|
|
480 ; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1{{$}}
|
|
|
481 ; GCN: ds_add_u32 v{{[0-9]+}}, [[ONE]]
|
|
|
482 ; GCN: s_endpgm
|
|
|
483 define amdgpu_kernel void @lds_atomic_add1_noret_i32(i32 addrspace(3)* %ptr) nounwind {
|
|
|
484 %result = atomicrmw add i32 addrspace(3)* %ptr, i32 1 seq_cst
|
|
|
485 ret void
|
|
|
486 }
|
|
|
487
|
|
|
488 ; FUNC-LABEL: {{^}}lds_atomic_add1_noret_i32_offset:
|
|
|
489 ; SICIVI-DAG: s_mov_b32 m0
|
|
|
490 ; GFX9-NOT: m0
|
|
|
491
|
|
|
492 ; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1{{$}}
|
|
|
493 ; GCN: ds_add_u32 v{{[0-9]+}}, [[ONE]] offset:16
|
|
|
494 ; GCN: s_endpgm
|
|
|
495 define amdgpu_kernel void @lds_atomic_add1_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
|
|
|
496 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
|
|
|
497 %result = atomicrmw add i32 addrspace(3)* %gep, i32 1 seq_cst
|
|
|
498 ret void
|
|
|
499 }
|
|
|
500
|
|
|
501 ; FUNC-LABEL: {{^}}lds_atomic_add1_noret_i32_bad_si_offset:
|
|
|
502 ; SICIVI: s_mov_b32 m0
|
|
|
503 ; GFX9-NOT: m0
|
|
|
504
|
|
|
505 ; SI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}}
|
|
|
506 ; CIVI: ds_add_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
|
|
|
507 ; GCN: s_endpgm
|
|
|
508 define amdgpu_kernel void @lds_atomic_add1_noret_i32_bad_si_offset(i32 addrspace(3)* %ptr, i32 %a, i32 %b) nounwind {
|
|
|
509 %sub = sub i32 %a, %b
|
|
|
510 %add = add i32 %sub, 4
|
|
|
511 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 %add
|
|
|
512 %result = atomicrmw add i32 addrspace(3)* %gep, i32 1 seq_cst
|
|
|
513 ret void
|
|
|
514 }
|
|
|
515
|
|
|
516 ; FUNC-LABEL: {{^}}lds_atomic_sub_noret_i32:
|
|
|
517 ; SICIVI: s_mov_b32 m0
|
|
|
518 ; GFX9-NOT: m0
|
|
|
519
|
|
|
520 ; GCN: ds_sub_u32
|
|
|
521 ; GCN: s_endpgm
|
|
|
522 define amdgpu_kernel void @lds_atomic_sub_noret_i32(i32 addrspace(3)* %ptr) nounwind {
|
|
|
523 %result = atomicrmw sub i32 addrspace(3)* %ptr, i32 4 seq_cst
|
|
|
524 ret void
|
|
|
525 }
|
|
|
526
|
|
|
527 ; FUNC-LABEL: {{^}}lds_atomic_sub_noret_i32_offset:
|
|
|
528 ; SICIVI: s_mov_b32 m0
|
|
|
529 ; GFX9-NOT: m0
|
|
|
530
|
|
|
531 ; GCN: ds_sub_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
|
|
|
532 ; GCN: s_endpgm
|
|
|
533 define amdgpu_kernel void @lds_atomic_sub_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
|
|
|
534 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
|
|
|
535 %result = atomicrmw sub i32 addrspace(3)* %gep, i32 4 seq_cst
|
|
|
536 ret void
|
|
|
537 }
|
|
|
538
|
|
|
539 ; FUNC-LABEL: {{^}}lds_atomic_sub1_noret_i32:
|
|
|
540 ; SICIVI-DAG: s_mov_b32 m0
|
|
|
541 ; GFX9-NOT: m0
|
|
|
542
|
|
|
543 ; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1{{$}}
|
|
|
544 ; GCN: ds_sub_u32 v{{[0-9]+}}, [[ONE]]
|
|
|
545 ; GCN: s_endpgm
|
|
|
546 define amdgpu_kernel void @lds_atomic_sub1_noret_i32(i32 addrspace(3)* %ptr) nounwind {
|
|
|
547 %result = atomicrmw sub i32 addrspace(3)* %ptr, i32 1 seq_cst
|
|
|
548 ret void
|
|
|
549 }
|
|
|
550
|
|
|
551 ; FUNC-LABEL: {{^}}lds_atomic_sub1_noret_i32_offset:
|
|
|
552 ; SICIVI-DAG: s_mov_b32 m0
|
|
|
553 ; GFX9-NOT: m0
|
|
|
554
|
|
|
555 ; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1{{$}}
|
|
|
556 ; GCN: ds_sub_u32 v{{[0-9]+}}, [[ONE]] offset:16
|
|
|
557 ; GCN: s_endpgm
|
|
|
558 define amdgpu_kernel void @lds_atomic_sub1_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
|
|
|
559 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
|
|
|
560 %result = atomicrmw sub i32 addrspace(3)* %gep, i32 1 seq_cst
|
|
|
561 ret void
|
|
|
562 }
|
|
|
563
|
|
|
564 ; FUNC-LABEL: {{^}}lds_atomic_and_noret_i32:
|
|
|
565 ; SICIVI: s_mov_b32 m0
|
|
|
566 ; GFX9-NOT: m0
|
|
|
567
|
|
|
568 ; GCN: ds_and_b32
|
|
|
569 ; GCN: s_endpgm
|
|
|
570 define amdgpu_kernel void @lds_atomic_and_noret_i32(i32 addrspace(3)* %ptr) nounwind {
|
|
|
571 %result = atomicrmw and i32 addrspace(3)* %ptr, i32 4 seq_cst
|
|
|
572 ret void
|
|
|
573 }
|
|
|
574
|
|
|
575 ; FUNC-LABEL: {{^}}lds_atomic_and_noret_i32_offset:
|
|
|
576 ; SICIVI: s_mov_b32 m0
|
|
|
577 ; GFX9-NOT: m0
|
|
|
578
|
|
|
579 ; GCN: ds_and_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
|
|
|
580 ; GCN: s_endpgm
|
|
|
581 define amdgpu_kernel void @lds_atomic_and_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
|
|
|
582 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
|
|
|
583 %result = atomicrmw and i32 addrspace(3)* %gep, i32 4 seq_cst
|
|
|
584 ret void
|
|
|
585 }
|
|
|
586
|
|
|
587 ; FUNC-LABEL: {{^}}lds_atomic_or_noret_i32:
|
|
|
588 ; SICIVI: s_mov_b32 m0
|
|
|
589 ; GFX9-NOT: m0
|
|
|
590
|
|
|
591 ; GCN: ds_or_b32
|
|
|
592 ; GCN: s_endpgm
|
|
|
593 define amdgpu_kernel void @lds_atomic_or_noret_i32(i32 addrspace(3)* %ptr) nounwind {
|
|
|
594 %result = atomicrmw or i32 addrspace(3)* %ptr, i32 4 seq_cst
|
|
|
595 ret void
|
|
|
596 }
|
|
|
597
|
|
|
598 ; FUNC-LABEL: {{^}}lds_atomic_or_noret_i32_offset:
|
|
|
599 ; SICIVI: s_mov_b32 m0
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600 ; GFX9-NOT: m0
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601
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602 ; GCN: ds_or_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
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603 ; GCN: s_endpgm
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604 define amdgpu_kernel void @lds_atomic_or_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
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605 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
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606 %result = atomicrmw or i32 addrspace(3)* %gep, i32 4 seq_cst
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607 ret void
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608 }
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609
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610 ; FUNC-LABEL: {{^}}lds_atomic_xor_noret_i32:
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611 ; SICIVI: s_mov_b32 m0
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612 ; GFX9-NOT: m0
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613
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614 ; GCN: ds_xor_b32
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615 ; GCN: s_endpgm
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616 define amdgpu_kernel void @lds_atomic_xor_noret_i32(i32 addrspace(3)* %ptr) nounwind {
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617 %result = atomicrmw xor i32 addrspace(3)* %ptr, i32 4 seq_cst
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618 ret void
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619 }
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620
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621 ; FUNC-LABEL: {{^}}lds_atomic_xor_noret_i32_offset:
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622 ; SICIVI: s_mov_b32 m0
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623 ; GFX9-NOT: m0
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624
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625 ; GCN: ds_xor_b32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
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626 ; GCN: s_endpgm
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627 define amdgpu_kernel void @lds_atomic_xor_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
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628 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
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629 %result = atomicrmw xor i32 addrspace(3)* %gep, i32 4 seq_cst
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630 ret void
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631 }
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632
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633 ; FIXME: There is no atomic nand instr
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634 ; XFUNC-LABEL: {{^}}lds_atomic_nand_noret_i32:uction, so we somehow need to expand this.
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635 ; define amdgpu_kernel void @lds_atomic_nand_noret_i32(i32 addrspace(3)* %ptr) nounwind {
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636 ; %result = atomicrmw nand i32 addrspace(3)* %ptr, i32 4 seq_cst
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637 ; ret void
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638 ; }
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639
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640 ; FUNC-LABEL: {{^}}lds_atomic_min_noret_i32:
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641 ; SICIVI: s_mov_b32 m0
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642 ; GFX9-NOT: m0
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643
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644 ; GCN: ds_min_i32
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645 ; GCN: s_endpgm
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646 define amdgpu_kernel void @lds_atomic_min_noret_i32(i32 addrspace(3)* %ptr) nounwind {
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647 %result = atomicrmw min i32 addrspace(3)* %ptr, i32 4 seq_cst
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648 ret void
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649 }
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650
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651 ; FUNC-LABEL: {{^}}lds_atomic_min_noret_i32_offset:
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652 ; SICIVI: s_mov_b32 m0
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653 ; GFX9-NOT: m0
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654
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655 ; GCN: ds_min_i32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
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656 ; GCN: s_endpgm
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657 define amdgpu_kernel void @lds_atomic_min_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
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658 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
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659 %result = atomicrmw min i32 addrspace(3)* %gep, i32 4 seq_cst
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660 ret void
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661 }
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662
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663 ; FUNC-LABEL: {{^}}lds_atomic_max_noret_i32:
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664 ; SICIVI: s_mov_b32 m0
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665 ; GFX9-NOT: m0
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666
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667 ; GCN: ds_max_i32
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668 ; GCN: s_endpgm
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669 define amdgpu_kernel void @lds_atomic_max_noret_i32(i32 addrspace(3)* %ptr) nounwind {
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670 %result = atomicrmw max i32 addrspace(3)* %ptr, i32 4 seq_cst
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671 ret void
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672 }
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673
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674 ; FUNC-LABEL: {{^}}lds_atomic_max_noret_i32_offset:
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675 ; SICIVI: s_mov_b32 m0
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676 ; GFX9-NOT: m0
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677
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678 ; GCN: ds_max_i32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
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679 ; GCN: s_endpgm
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680 define amdgpu_kernel void @lds_atomic_max_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
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681 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
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682 %result = atomicrmw max i32 addrspace(3)* %gep, i32 4 seq_cst
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683 ret void
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684 }
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685
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686 ; FUNC-LABEL: {{^}}lds_atomic_umin_noret_i32:
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687 ; SICIVI: s_mov_b32 m0
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688 ; GFX9-NOT: m0
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689
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690 ; GCN: ds_min_u32
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691 ; GCN: s_endpgm
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692 define amdgpu_kernel void @lds_atomic_umin_noret_i32(i32 addrspace(3)* %ptr) nounwind {
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693 %result = atomicrmw umin i32 addrspace(3)* %ptr, i32 4 seq_cst
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|
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694 ret void
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695 }
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696
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697 ; FUNC-LABEL: {{^}}lds_atomic_umin_noret_i32_offset:
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698 ; SICIVI: s_mov_b32 m0
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699 ; GFX9-NOT: m0
|
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|
700
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701 ; GCN: ds_min_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
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702 ; GCN: s_endpgm
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703 define amdgpu_kernel void @lds_atomic_umin_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
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704 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
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|
705 %result = atomicrmw umin i32 addrspace(3)* %gep, i32 4 seq_cst
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706 ret void
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707 }
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708
|
|
|
709 ; FUNC-LABEL: {{^}}lds_atomic_umax_noret_i32:
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|
710 ; SICIVI: s_mov_b32 m0
|
|
|
711 ; GFX9-NOT: m0
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712
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713 ; GCN: ds_max_u32
|
|
|
714 ; GCN: s_endpgm
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715 define amdgpu_kernel void @lds_atomic_umax_noret_i32(i32 addrspace(3)* %ptr) nounwind {
|
|
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716 %result = atomicrmw umax i32 addrspace(3)* %ptr, i32 4 seq_cst
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|
|
717 ret void
|
|
|
718 }
|
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719
|
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720 ; FUNC-LABEL: {{^}}lds_atomic_umax_noret_i32_offset:
|
|
|
721 ; SICIVI: s_mov_b32 m0
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722 ; GFX9-NOT: m0
|
|
|
723
|
|
|
724 ; GCN: ds_max_u32 v{{[0-9]+}}, v{{[0-9]+}} offset:16
|
|
|
725 ; GCN: s_endpgm
|
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726 define amdgpu_kernel void @lds_atomic_umax_noret_i32_offset(i32 addrspace(3)* %ptr) nounwind {
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|
|
727 %gep = getelementptr i32, i32 addrspace(3)* %ptr, i32 4
|
|
|
728 %result = atomicrmw umax i32 addrspace(3)* %gep, i32 4 seq_cst
|
|
|
729 ret void
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730 }
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