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150
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1 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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2 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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3 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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4
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5
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6 ; FUNC-LABEL: {{^}}or_v2i32:
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7 ; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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8 ; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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9
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10 ; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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11 ; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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12 define amdgpu_kernel void @or_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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13 %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
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14 %a = load <2 x i32>, <2 x i32> addrspace(1) * %in
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15 %b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr
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16 %result = or <2 x i32> %a, %b
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17 store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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18 ret void
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19 }
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20
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21 ; FUNC-LABEL: {{^}}or_v4i32:
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22 ; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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23 ; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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24 ; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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25 ; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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26
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27 ; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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28 ; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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29 ; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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30 ; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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31 define amdgpu_kernel void @or_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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32 %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
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33 %a = load <4 x i32>, <4 x i32> addrspace(1) * %in
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34 %b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr
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35 %result = or <4 x i32> %a, %b
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36 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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37 ret void
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38 }
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39
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40 ; FUNC-LABEL: {{^}}scalar_or_i32:
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41 ; SI: s_or_b32
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42 define amdgpu_kernel void @scalar_or_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
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43 %or = or i32 %a, %b
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44 store i32 %or, i32 addrspace(1)* %out
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45 ret void
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46 }
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47
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48 ; FUNC-LABEL: {{^}}vector_or_i32:
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49 ; SI: v_or_b32_e32 v{{[0-9]}}
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50 define amdgpu_kernel void @vector_or_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 %b) {
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51 %loada = load i32, i32 addrspace(1)* %a
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52 %or = or i32 %loada, %b
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53 store i32 %or, i32 addrspace(1)* %out
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54 ret void
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55 }
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56
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57 ; FUNC-LABEL: {{^}}scalar_or_literal_i32:
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58 ; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x1869f
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59 define amdgpu_kernel void @scalar_or_literal_i32(i32 addrspace(1)* %out, i32 %a) {
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60 %or = or i32 %a, 99999
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61 store i32 %or, i32 addrspace(1)* %out, align 4
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62 ret void
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63 }
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64
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65 ; FUNC-LABEL: {{^}}scalar_or_literal_i64:
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66 ; SI: s_load_dwordx2 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}}
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67 ; SI-DAG: s_or_b32 s[[RES_HI:[0-9]+]], s[[HI]], 0xf237b
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68 ; SI-DAG: s_or_b32 s[[RES_LO:[0-9]+]], s[[LO]], 0x3039
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69 ; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[RES_LO]]
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70 ; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[RES_HI]]
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71 define amdgpu_kernel void @scalar_or_literal_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a) {
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72 %or = or i64 %a, 4261135838621753
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73 store i64 %or, i64 addrspace(1)* %out
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74 ret void
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75 }
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76
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77 ; FUNC-LABEL: {{^}}scalar_or_literal_multi_use_i64:
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78 ; SI: s_load_dwordx2 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}}
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79 ; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0xf237b
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80 ; SI-DAG: s_movk_i32 s[[K_LO:[0-9]+]], 0x3039
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81 ; SI: s_or_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[K_LO]]:[[K_HI]]{{\]}}
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82
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83 ; SI: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, s[[K_LO]]
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84 ; SI: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, s[[K_HI]]
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85 define amdgpu_kernel void @scalar_or_literal_multi_use_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a, [8 x i32], i64 %b) {
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86 %or = or i64 %a, 4261135838621753
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87 store i64 %or, i64 addrspace(1)* %out
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88
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89 %foo = add i64 %b, 4261135838621753
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90 store volatile i64 %foo, i64 addrspace(1)* undef
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91 ret void
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92 }
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93
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94 ; FUNC-LABEL: {{^}}scalar_or_inline_imm_i64:
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95 ; SI: s_load_dwordx2 s{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}}
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96 ; SI-NOT: or_b32
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97 ; SI: s_or_b32 s[[VAL_LO]], s[[VAL_LO]], 63
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98 ; SI-NOT: or_b32
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99 ; SI: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[VAL_LO]]
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100 ; SI-NOT: or_b32
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101 ; SI: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[VAL_HI]]
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102 ; SI-NOT: or_b32
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103 ; SI: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}}
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104 define amdgpu_kernel void @scalar_or_inline_imm_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a) {
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105 %or = or i64 %a, 63
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106 store i64 %or, i64 addrspace(1)* %out
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107 ret void
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108 }
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109
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110 ; FUNC-LABEL: {{^}}scalar_or_inline_imm_multi_use_i64:
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111 ; SI-NOT: or_b32
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112 ; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 63
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113 ; SI-NOT: or_b32
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114 define amdgpu_kernel void @scalar_or_inline_imm_multi_use_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
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115 %or = or i64 %a, 63
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116 store i64 %or, i64 addrspace(1)* %out
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117 %foo = add i64 %b, 63
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118 store volatile i64 %foo, i64 addrspace(1)* undef
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119 ret void
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120 }
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121
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122 ; FUNC-LABEL: {{^}}scalar_or_neg_inline_imm_i64:
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123 ; SI-DAG: s_load_dword [[VAL:s[0-9]+]]
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124 ; SI-DAG: s_or_b32 [[VAL]], [[VAL]], -8
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125 ; SI-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], -1{{$}}
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126 ; SI-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[VAL]]
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127 ; SI: buffer_store_dwordx2 v{{\[}}[[V_LO]]:[[V_HI]]{{\]}}
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128 define amdgpu_kernel void @scalar_or_neg_inline_imm_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a) {
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129 %or = or i64 %a, -8
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130 store i64 %or, i64 addrspace(1)* %out
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131 ret void
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132 }
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133
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134 ; FUNC-LABEL: {{^}}vector_or_literal_i32:
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135 ; SI: v_or_b32_e32 v{{[0-9]+}}, 0xffff, v{{[0-9]+}}
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136 define amdgpu_kernel void @vector_or_literal_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) {
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137 %loada = load i32, i32 addrspace(1)* %a, align 4
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138 %or = or i32 %loada, 65535
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139 store i32 %or, i32 addrspace(1)* %out, align 4
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140 ret void
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141 }
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142
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143 ; FUNC-LABEL: {{^}}vector_or_inline_immediate_i32:
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144 ; SI: v_or_b32_e32 v{{[0-9]+}}, 4, v{{[0-9]+}}
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145 define amdgpu_kernel void @vector_or_inline_immediate_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %a, i32 addrspace(1)* %b) {
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146 %loada = load i32, i32 addrspace(1)* %a, align 4
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147 %or = or i32 %loada, 4
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148 store i32 %or, i32 addrspace(1)* %out, align 4
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149 ret void
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150 }
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151
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152 ; FUNC-LABEL: {{^}}scalar_or_i64:
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153 ; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
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154 ; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z
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155
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156 ; SI: s_or_b64
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157 define amdgpu_kernel void @scalar_or_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
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158 %or = or i64 %a, %b
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159 store i64 %or, i64 addrspace(1)* %out
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160 ret void
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161 }
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162
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163 ; FUNC-LABEL: {{^}}vector_or_i64:
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164 ; SI: v_or_b32_e32 v{{[0-9]}}
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165 ; SI: v_or_b32_e32 v{{[0-9]}}
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166 define amdgpu_kernel void @vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
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167 %loada = load i64, i64 addrspace(1)* %a, align 8
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168 %loadb = load i64, i64 addrspace(1)* %b, align 8
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169 %or = or i64 %loada, %loadb
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170 store i64 %or, i64 addrspace(1)* %out
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171 ret void
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172 }
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173
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174 ; FUNC-LABEL: {{^}}scalar_vector_or_i64:
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175 ; SI: v_or_b32_e32 v{{[0-9]}}
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176 ; SI: v_or_b32_e32 v{{[0-9]}}
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177 define amdgpu_kernel void @scalar_vector_or_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 %b) {
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178 %loada = load i64, i64 addrspace(1)* %a
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179 %or = or i64 %loada, %b
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180 store i64 %or, i64 addrspace(1)* %out
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181 ret void
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182 }
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183
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184 ; FUNC-LABEL: {{^}}vector_or_i64_loadimm:
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185 ; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}},
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186 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0xdf77987f, v[[LO_VREG]]
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187 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0x146f, v[[HI_VREG]]
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188 ; SI: s_endpgm
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189 define amdgpu_kernel void @vector_or_i64_loadimm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
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190 %loada = load i64, i64 addrspace(1)* %a, align 8
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191 %or = or i64 %loada, 22470723082367
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192 store i64 %or, i64 addrspace(1)* %out
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193 ret void
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194 }
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195
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196 ; FIXME: The or 0 should really be removed.
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197 ; FUNC-LABEL: {{^}}vector_or_i64_imm:
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198 ; SI: buffer_load_dwordx2 v{{\[}}[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]{{\]}},
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199 ; SI: v_or_b32_e32 v[[LO_RESULT:[0-9]+]], 8, v[[LO_VREG]]
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200 ; SI-NOT: v_or_b32_e32 {{v[0-9]+}}, 0
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201 ; SI: buffer_store_dwordx2 v{{\[}}[[LO_RESULT]]:[[HI_VREG]]{{\]}}
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202 ; SI: s_endpgm
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203 define amdgpu_kernel void @vector_or_i64_imm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
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204 %loada = load i64, i64 addrspace(1)* %a, align 8
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205 %or = or i64 %loada, 8
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206 store i64 %or, i64 addrspace(1)* %out
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207 ret void
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208 }
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209
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210 ; FUNC-LABEL: {{^}}vector_or_i64_neg_inline_imm:
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211 ; SI-DAG: buffer_load_dword v[[LO_VREG:[0-9]+]]
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212 ; SI-DAG: v_or_b32_e32 v[[RES_LO:[0-9]+]], -8, v[[LO_VREG]]
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213 ; SI-DAG: v_mov_b32_e32 v[[RES_HI:[0-9]+]], -1{{$}}
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214 ; SI: buffer_store_dwordx2 v{{\[}}[[RES_LO]]:[[RES_HI]]{{\]}}
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215 ; SI: s_endpgm
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216 define amdgpu_kernel void @vector_or_i64_neg_inline_imm(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
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217 %loada = load i64, i64 addrspace(1)* %a, align 8
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218 %or = or i64 %loada, -8
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219 store i64 %or, i64 addrspace(1)* %out
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220 ret void
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221 }
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222
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223 ; FUNC-LABEL: {{^}}vector_or_i64_neg_literal:
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224 ; SI-DAG: buffer_load_dword v[[LO_VREG:[0-9]+]]
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225 ; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, -1{{$}}
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226 ; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0xffffff38, v[[LO_VREG]]
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227 ; SI: buffer_store_dwordx2
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228 ; SI: s_endpgm
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229 define amdgpu_kernel void @vector_or_i64_neg_literal(i64 addrspace(1)* %out, i64 addrspace(1)* %a, i64 addrspace(1)* %b) {
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230 %loada = load i64, i64 addrspace(1)* %a, align 8
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231 %or = or i64 %loada, -200
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232 store i64 %or, i64 addrspace(1)* %out
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233 ret void
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234 }
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235
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236 ; FUNC-LABEL: {{^}}trunc_i64_or_to_i32:
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237 ; SI: s_load_dword s[[SREG0:[0-9]+]]
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238 ; SI: s_load_dword s[[SREG1:[0-9]+]]
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239 ; SI: s_or_b32 s[[SRESULT:[0-9]+]], s[[SREG1]], s[[SREG0]]
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240 ; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], s[[SRESULT]]
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241 ; SI: buffer_store_dword [[VRESULT]],
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242 define amdgpu_kernel void @trunc_i64_or_to_i32(i32 addrspace(1)* %out, [8 x i32], i64 %a, [8 x i32], i64 %b) {
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243 %add = or i64 %b, %a
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244 %trunc = trunc i64 %add to i32
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245 store i32 %trunc, i32 addrspace(1)* %out, align 8
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246 ret void
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247 }
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248
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249 ; FUNC-LABEL: {{^}}or_i1:
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250 ; EG: OR_INT * {{\** *}}T{{[0-9]+\.[XYZW], PS, PV\.[XYZW]}}
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251
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252 ; SI: s_or_b64 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], vcc
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253 define amdgpu_kernel void @or_i1(i32 addrspace(1)* %out, float addrspace(1)* %in0, float addrspace(1)* %in1) {
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254 %a = load float, float addrspace(1)* %in0
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255 %b = load float, float addrspace(1)* %in1
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256 %acmp = fcmp oge float %a, 0.000000e+00
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257 %bcmp = fcmp oge float %b, 0.000000e+00
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258 %or = or i1 %acmp, %bcmp
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259 %result = zext i1 %or to i32
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260 store i32 %result, i32 addrspace(1)* %out
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261 ret void
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262 }
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263
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264 ; FUNC-LABEL: {{^}}s_or_i1:
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265 ; SI: s_or_b64 s[{{[0-9]+:[0-9]+}}], vcc, s[{{[0-9]+:[0-9]+}}]
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266 define amdgpu_kernel void @s_or_i1(i1 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) {
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267 %cmp0 = icmp eq i32 %a, %b
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268 %cmp1 = icmp eq i32 %c, %d
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269 %or = or i1 %cmp0, %cmp1
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270 store i1 %or, i1 addrspace(1)* %out
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271 ret void
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272 }
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