annotate llvm/test/CodeGen/AMDGPU/salu-to-valu.ll @ 223:5f17cb93ff66 llvm-original

LLVM13 (2021/7/18)
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Sun, 18 Jul 2021 22:43:00 +0900
parents 79ff65ed7e25
children c4bab56944e8
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1 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=SI %s
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2 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=CI -check-prefix=CI-NOHSA %s
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3 ; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn--amdhsa -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI --check-prefix=GCN-HSA %s
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4
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5 declare i32 @llvm.amdgcn.workitem.id.x() #0
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6 declare i32 @llvm.amdgcn.workitem.id.y() #0
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7
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8 ; In this test both the pointer and the offset operands to the
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9 ; BUFFER_LOAD instructions end up being stored in vgprs. This
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10 ; requires us to add the pointer and offset together, store the
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11 ; result in the offset operand (vaddr), and then store 0 in an
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12 ; sgpr register pair and use that for the pointer operand
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13 ; (low 64-bits of srsrc).
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14
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15 ; GCN-LABEL: {{^}}mubuf:
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16
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17 ; Make sure we aren't using VGPRs for the source operand of s_mov_b64
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18 ; GCN-NOT: s_mov_b64 s[{{[0-9]+:[0-9]+}}], v
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19
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20 ; Make sure we aren't using VGPR's for the srsrc operand of BUFFER_LOAD_*
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21 ; instructions
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22 ; GCN-NOHSA: buffer_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64
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23 ; GCN-NOHSA: buffer_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64
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24 ; GCN-HSA: flat_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}
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25 ; GCN-HSA: flat_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}
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26
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27 define amdgpu_kernel void @mubuf(i32 addrspace(1)* %out, i8 addrspace(1)* %in) #1 {
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28 entry:
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29 %tmp = call i32 @llvm.amdgcn.workitem.id.x()
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30 %tmp1 = call i32 @llvm.amdgcn.workitem.id.y()
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31 %tmp2 = sext i32 %tmp to i64
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32 %tmp3 = sext i32 %tmp1 to i64
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33 br label %loop
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34
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35 loop: ; preds = %loop, %entry
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36 %tmp4 = phi i64 [ 0, %entry ], [ %tmp5, %loop ]
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37 %tmp5 = add i64 %tmp2, %tmp4
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38 %tmp6 = getelementptr i8, i8 addrspace(1)* %in, i64 %tmp5
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39 %tmp7 = load i8, i8 addrspace(1)* %tmp6, align 1
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40 %tmp8 = or i64 %tmp5, 1
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41 %tmp9 = getelementptr i8, i8 addrspace(1)* %in, i64 %tmp8
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42 %tmp10 = load i8, i8 addrspace(1)* %tmp9, align 1
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43 %tmp11 = add i8 %tmp7, %tmp10
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44 %tmp12 = sext i8 %tmp11 to i32
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45 store i32 %tmp12, i32 addrspace(1)* %out
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46 %tmp13 = icmp slt i64 %tmp5, 10
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47 br i1 %tmp13, label %loop, label %done
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48
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49 done: ; preds = %loop
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50 ret void
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51 }
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52
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53 ; Test moving an SMRD instruction to the VALU
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54 ; FIXME: movs can be moved before nop to reduce count
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55
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56 ; GCN-LABEL: {{^}}smrd_valu:
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57 ; SI: s_movk_i32 [[OFFSET:s[0-9]+]], 0x2ee0
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58 ; GCN: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
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59 ; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
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60 ; SI: s_mov_b32
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61 ; SI: s_nop 1
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62 ; SI: s_load_dword [[OUT:s[0-9]+]], s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, [[OFFSET]]
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63
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64 ; CI: s_load_dword [[OUT:s[0-9]+]], s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0xbb8
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65 ; GCN: v_mov_b32_e32 [[V_OUT:v[0-9]+]], [[OUT]]
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66 ; GCN-NOHSA: buffer_store_dword [[V_OUT]]
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67 ; GCN-HSA: flat_store_dword {{.*}}, [[V_OUT]]
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68 define amdgpu_kernel void @smrd_valu(i32 addrspace(4)* addrspace(1)* %in, i32 %a, i32 %b, i32 addrspace(1)* %out) #1 {
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69 entry:
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70 %tmp = icmp ne i32 %a, 0
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71 br i1 %tmp, label %if, label %else
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72
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73 if: ; preds = %entry
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74 %tmp1 = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(1)* %in
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75 br label %endif
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76
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77 else: ; preds = %entry
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78 %tmp2 = getelementptr i32 addrspace(4)*, i32 addrspace(4)* addrspace(1)* %in
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79 %tmp3 = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(1)* %tmp2
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80 br label %endif
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81
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82 endif: ; preds = %else, %if
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83 %tmp4 = phi i32 addrspace(4)* [ %tmp1, %if ], [ %tmp3, %else ]
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84 %tmp5 = getelementptr i32, i32 addrspace(4)* %tmp4, i32 3000
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85 %tmp6 = load i32, i32 addrspace(4)* %tmp5
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86 store i32 %tmp6, i32 addrspace(1)* %out
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87 ret void
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88 }
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89
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90 ; Test moving an SMRD with an immediate offset to the VALU
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91
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92 ; GCN-LABEL: {{^}}smrd_valu2:
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93 ; GCN-NOHSA-NOT: v_add
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94 ; GCN-NOHSA: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:16{{$}}
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95 ; GCN-HSA: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
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96 define amdgpu_kernel void @smrd_valu2(i32 addrspace(1)* %out, [8 x i32] addrspace(4)* %in) #1 {
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97 entry:
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98 %tmp = call i32 @llvm.amdgcn.workitem.id.x()
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99 %tmp1 = add i32 %tmp, 4
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100 %tmp2 = getelementptr [8 x i32], [8 x i32] addrspace(4)* %in, i32 %tmp, i32 4
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101 %tmp3 = load i32, i32 addrspace(4)* %tmp2
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102 store i32 %tmp3, i32 addrspace(1)* %out
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103 ret void
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104 }
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105
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106 ; Use a big offset that will use the SMRD literal offset on CI
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107 ; GCN-LABEL: {{^}}smrd_valu_ci_offset:
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108 ; GCN-NOHSA-NOT: v_add
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109 ; GCN-NOHSA: s_movk_i32 [[OFFSET:s[0-9]+]], 0x4e20{{$}}
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110 ; GCN-NOHSA-NOT: v_add
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111 ; GCN-NOHSA: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET]] addr64{{$}}
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112 ; GCN-NOHSA: v_add_i32_e32
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113 ; GCN-NOHSA: buffer_store_dword
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114 ; GCN-HSA: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
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115 ; GCN-HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}
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116 define amdgpu_kernel void @smrd_valu_ci_offset(i32 addrspace(1)* %out, i32 addrspace(4)* %in, i32 %c) #1 {
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117 entry:
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118 %tmp = call i32 @llvm.amdgcn.workitem.id.x()
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119 %tmp2 = getelementptr i32, i32 addrspace(4)* %in, i32 %tmp
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120 %tmp3 = getelementptr i32, i32 addrspace(4)* %tmp2, i32 5000
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121 %tmp4 = load i32, i32 addrspace(4)* %tmp3
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122 %tmp5 = add i32 %tmp4, %c
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123 store i32 %tmp5, i32 addrspace(1)* %out
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124 ret void
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125 }
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126
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127 ; GCN-LABEL: {{^}}smrd_valu_ci_offset_x2:
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128 ; GCN-NOHSA-NOT: v_add
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129 ; GCN-NOHSA: s_mov_b32 [[OFFSET:s[0-9]+]], 0x9c40{{$}}
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130 ; GCN-NOHSA-NOT: v_add
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131 ; GCN-NOHSA: buffer_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET]] addr64{{$}}
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132 ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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133 ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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134 ; GCN-NOHSA: buffer_store_dwordx2
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135 ; GCN-HSA: flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
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136 define amdgpu_kernel void @smrd_valu_ci_offset_x2(i64 addrspace(1)* %out, i64 addrspace(4)* %in, i64 %c) #1 {
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137 entry:
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138 %tmp = call i32 @llvm.amdgcn.workitem.id.x()
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139 %tmp2 = getelementptr i64, i64 addrspace(4)* %in, i32 %tmp
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140 %tmp3 = getelementptr i64, i64 addrspace(4)* %tmp2, i32 5000
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141 %tmp4 = load i64, i64 addrspace(4)* %tmp3
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142 %tmp5 = or i64 %tmp4, %c
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143 store i64 %tmp5, i64 addrspace(1)* %out
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144 ret void
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145 }
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146
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147 ; GCN-LABEL: {{^}}smrd_valu_ci_offset_x4:
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148 ; GCN-NOHSA-NOT: v_add
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149 ; GCN-NOHSA: s_movk_i32 [[OFFSET:s[0-9]+]], 0x4d20{{$}}
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150 ; GCN-NOHSA-NOT: v_add
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151 ; GCN-NOHSA: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET]] addr64{{$}}
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152 ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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153 ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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154 ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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155 ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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156 ; GCN-NOHSA: buffer_store_dwordx4
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157 ; GCN-HSA: flat_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
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158 define amdgpu_kernel void @smrd_valu_ci_offset_x4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(4)* %in, <4 x i32> %c) #1 {
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159 entry:
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160 %tmp = call i32 @llvm.amdgcn.workitem.id.x()
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161 %tmp2 = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %in, i32 %tmp
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162 %tmp3 = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %tmp2, i32 1234
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163 %tmp4 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp3
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164 %tmp5 = or <4 x i32> %tmp4, %c
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165 store <4 x i32> %tmp5, <4 x i32> addrspace(1)* %out
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166 ret void
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167 }
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168
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169 ; Original scalar load uses SGPR offset on SI and 32-bit literal on
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170 ; CI.
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171
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172 ; GCN-LABEL: {{^}}smrd_valu_ci_offset_x8:
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173 ; GCN-NOHSA-DAG: s_mov_b32 [[OFFSET0:s[0-9]+]], 0x9a40{{$}}
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174 ; CI-NOHSA-DAG: s_mov_b32 [[OFFSET1:s[0-9]+]], 0x9a50{{$}}
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175 ; CI-NOHSA-NOT: v_add
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176 ; SI: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:16
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177 ; CI-NOHSA: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET1]] addr64{{$}}
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178 ; GCN-NOHSA: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET0]] addr64{{$}}
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179
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180 ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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181 ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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182 ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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183 ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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184 ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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185 ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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186 ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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187 ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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188 ; GCN-NOHSA: buffer_store_dwordx4
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189 ; GCN-NOHSA: buffer_store_dwordx4
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190 ; GCN-HSA: flat_load_dwordx4
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191 ; GCN-HSA: flat_load_dwordx4
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192 define amdgpu_kernel void @smrd_valu_ci_offset_x8(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(4)* %in, <8 x i32> %c) #1 {
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193 entry:
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194 %tmp = call i32 @llvm.amdgcn.workitem.id.x()
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195 %tmp2 = getelementptr <8 x i32>, <8 x i32> addrspace(4)* %in, i32 %tmp
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196 %tmp3 = getelementptr <8 x i32>, <8 x i32> addrspace(4)* %tmp2, i32 1234
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197 %tmp4 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp3
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198 %tmp5 = or <8 x i32> %tmp4, %c
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199 store <8 x i32> %tmp5, <8 x i32> addrspace(1)* %out
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200 ret void
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201 }
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202
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203 ; GCN-LABEL: {{^}}smrd_valu_ci_offset_x16:
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204
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205 ; SI: s_mov_b32 {{s[0-9]+}}, 0x13480
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206 ; SI: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:32
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207 ; SI: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:48
221
79ff65ed7e25 LLVM12 Original
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 173
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208 ; SI: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:16
150
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209 ; SI: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], {{s[0-9]+}} addr64
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210 ; CI-NOHSA-DAG: s_mov_b32 [[OFFSET0:s[0-9]+]], 0x13480{{$}}
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211 ; CI-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET0]] addr64{{$}}
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212 ; CI-NOHSA-DAG: s_mov_b32 [[OFFSET1:s[0-9]+]], 0x13490{{$}}
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213 ; CI-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET1]] addr64{{$}}
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214 ; CI-NOHSA-DAG: s_mov_b32 [[OFFSET2:s[0-9]+]], 0x134a0{{$}}
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215 ; CI-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET2]] addr64{{$}}
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216 ; CI-NOHSA-DAG: s_mov_b32 [[OFFSET3:s[0-9]+]], 0x134b0{{$}}
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217 ; CI-NOHSA-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET3]] addr64{{$}}
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218
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219 ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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220 ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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221 ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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222 ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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223 ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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224 ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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225 ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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226 ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
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227 ; GCN-NOHSA: buffer_store_dwordx4
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228 ; GCN-NOHSA: buffer_store_dwordx4
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229 ; GCN-NOHSA: buffer_store_dwordx4
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230 ; GCN-NOHSA: buffer_store_dwordx4
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231
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232 ; GCN-HSA: flat_load_dwordx4
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233 ; GCN-HSA: flat_load_dwordx4
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234 ; GCN-HSA: flat_load_dwordx4
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235 ; GCN-HSA: flat_load_dwordx4
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236
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237 ; GCN: s_endpgm
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238 define amdgpu_kernel void @smrd_valu_ci_offset_x16(<16 x i32> addrspace(1)* %out, <16 x i32> addrspace(4)* %in, <16 x i32> %c) #1 {
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239 entry:
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240 %tmp = call i32 @llvm.amdgcn.workitem.id.x()
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241 %tmp2 = getelementptr <16 x i32>, <16 x i32> addrspace(4)* %in, i32 %tmp
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242 %tmp3 = getelementptr <16 x i32>, <16 x i32> addrspace(4)* %tmp2, i32 1234
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243 %tmp4 = load <16 x i32>, <16 x i32> addrspace(4)* %tmp3
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244 %tmp5 = or <16 x i32> %tmp4, %c
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245 store <16 x i32> %tmp5, <16 x i32> addrspace(1)* %out
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246 ret void
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247 }
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248
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249 ; GCN-LABEL: {{^}}smrd_valu2_salu_user:
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250 ; GCN-NOHSA: buffer_load_dword [[MOVED:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
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251 ; GCN-HSA: flat_load_dword [[MOVED:v[0-9]+]], v[{{[0-9+:[0-9]+}}]
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252 ; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, s{{[0-9]+}}, [[MOVED]]
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253 ; GCN-NOHSA: buffer_store_dword [[ADD]]
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254 ; GCN-HSA: flat_store_dword {{.*}}, [[ADD]]
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255 define amdgpu_kernel void @smrd_valu2_salu_user(i32 addrspace(1)* %out, [8 x i32] addrspace(4)* %in, i32 %a) #1 {
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256 entry:
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257 %tmp = call i32 @llvm.amdgcn.workitem.id.x()
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258 %tmp1 = add i32 %tmp, 4
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259 %tmp2 = getelementptr [8 x i32], [8 x i32] addrspace(4)* %in, i32 %tmp, i32 4
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260 %tmp3 = load i32, i32 addrspace(4)* %tmp2
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261 %tmp4 = add i32 %tmp3, %a
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262 store i32 %tmp4, i32 addrspace(1)* %out
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263 ret void
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264 }
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265
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266 ; GCN-LABEL: {{^}}smrd_valu2_max_smrd_offset:
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267 ; GCN-NOHSA: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:1020{{$}}
173
0572611fdcc8 reorgnization done
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
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268 ; GCN-HSA: flat_load_dword v{{[0-9]}}, v[{{[0-9]+:[0-9]+}}]
150
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269 define amdgpu_kernel void @smrd_valu2_max_smrd_offset(i32 addrspace(1)* %out, [1024 x i32] addrspace(4)* %in) #1 {
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270 entry:
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271 %tmp = call i32 @llvm.amdgcn.workitem.id.x()
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272 %tmp1 = add i32 %tmp, 4
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273 %tmp2 = getelementptr [1024 x i32], [1024 x i32] addrspace(4)* %in, i32 %tmp, i32 255
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274 %tmp3 = load i32, i32 addrspace(4)* %tmp2
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275 store i32 %tmp3, i32 addrspace(1)* %out
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276 ret void
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277 }
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278
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279 ; GCN-LABEL: {{^}}smrd_valu2_mubuf_offset:
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280 ; GCN-NOHSA-NOT: v_add
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281 ; GCN-NOHSA: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:1024{{$}}
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282 ; GCN-HSA: flat_load_dword v{{[0-9]}}, v[{{[0-9]+:[0-9]+}}]
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283 define amdgpu_kernel void @smrd_valu2_mubuf_offset(i32 addrspace(1)* %out, [1024 x i32] addrspace(4)* %in) #1 {
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284 entry:
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285 %tmp = call i32 @llvm.amdgcn.workitem.id.x()
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286 %tmp1 = add i32 %tmp, 4
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287 %tmp2 = getelementptr [1024 x i32], [1024 x i32] addrspace(4)* %in, i32 %tmp, i32 256
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288 %tmp3 = load i32, i32 addrspace(4)* %tmp2
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289 store i32 %tmp3, i32 addrspace(1)* %out
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290 ret void
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291 }
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292
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293 ; GCN-LABEL: {{^}}s_load_imm_v8i32:
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294 ; GCN-NOHSA: buffer_load_dwordx4
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295 ; GCN-NOHSA: buffer_load_dwordx4
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296 ; GCN-HSA: flat_load_dwordx4
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297 ; GCN-HSA: flat_load_dwordx4
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298 define amdgpu_kernel void @s_load_imm_v8i32(<8 x i32> addrspace(1)* %out, i32 addrspace(4)* nocapture readonly %in) #1 {
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299 entry:
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300 %tmp0 = tail call i32 @llvm.amdgcn.workitem.id.x()
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301 %tmp1 = getelementptr inbounds i32, i32 addrspace(4)* %in, i32 %tmp0
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302 %tmp2 = bitcast i32 addrspace(4)* %tmp1 to <8 x i32> addrspace(4)*
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303 %tmp3 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp2, align 4
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304 store <8 x i32> %tmp3, <8 x i32> addrspace(1)* %out, align 32
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305 ret void
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306 }
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307
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308 ; GCN-LABEL: {{^}}s_load_imm_v8i32_salu_user:
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309 ; GCN-NOHSA: buffer_load_dwordx4
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310 ; GCN-NOHSA: buffer_load_dwordx4
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311 ; GCN-NOHSA: v_add_i32_e32
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312 ; GCN-NOHSA: v_add_i32_e32
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313 ; GCN-NOHSA: v_add_i32_e32
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314 ; GCN-NOHSA: v_add_i32_e32
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315 ; GCN-NOHSA: v_add_i32_e32
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316 ; GCN-NOHSA: v_add_i32_e32
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317 ; GCN-NOHSA: v_add_i32_e32
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318 ; GCN-NOHSA: buffer_store_dword
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319 ; GCN-HSA: flat_load_dwordx4
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320 ; GCN-HSA: flat_load_dwordx4
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321 define amdgpu_kernel void @s_load_imm_v8i32_salu_user(i32 addrspace(1)* %out, i32 addrspace(4)* nocapture readonly %in) #1 {
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322 entry:
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323 %tmp0 = tail call i32 @llvm.amdgcn.workitem.id.x()
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324 %tmp1 = getelementptr inbounds i32, i32 addrspace(4)* %in, i32 %tmp0
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325 %tmp2 = bitcast i32 addrspace(4)* %tmp1 to <8 x i32> addrspace(4)*
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326 %tmp3 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp2, align 4
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327
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328 %elt0 = extractelement <8 x i32> %tmp3, i32 0
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329 %elt1 = extractelement <8 x i32> %tmp3, i32 1
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330 %elt2 = extractelement <8 x i32> %tmp3, i32 2
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331 %elt3 = extractelement <8 x i32> %tmp3, i32 3
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332 %elt4 = extractelement <8 x i32> %tmp3, i32 4
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333 %elt5 = extractelement <8 x i32> %tmp3, i32 5
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334 %elt6 = extractelement <8 x i32> %tmp3, i32 6
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335 %elt7 = extractelement <8 x i32> %tmp3, i32 7
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336
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337 %add0 = add i32 %elt0, %elt1
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338 %add1 = add i32 %add0, %elt2
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339 %add2 = add i32 %add1, %elt3
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340 %add3 = add i32 %add2, %elt4
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341 %add4 = add i32 %add3, %elt5
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342 %add5 = add i32 %add4, %elt6
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343 %add6 = add i32 %add5, %elt7
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344
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345 store i32 %add6, i32 addrspace(1)* %out
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346 ret void
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347 }
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348
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349 ; GCN-LABEL: {{^}}s_load_imm_v16i32:
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350 ; GCN-NOHSA: buffer_load_dwordx4
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351 ; GCN-NOHSA: buffer_load_dwordx4
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352 ; GCN-NOHSA: buffer_load_dwordx4
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353 ; GCN-NOHSA: buffer_load_dwordx4
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354 ; GCN-HSA: flat_load_dwordx4
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355 ; GCN-HSA: flat_load_dwordx4
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356 ; GCN-HSA: flat_load_dwordx4
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357 ; GCN-HSA: flat_load_dwordx4
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358 define amdgpu_kernel void @s_load_imm_v16i32(<16 x i32> addrspace(1)* %out, i32 addrspace(4)* nocapture readonly %in) #1 {
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359 entry:
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360 %tmp0 = tail call i32 @llvm.amdgcn.workitem.id.x()
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361 %tmp1 = getelementptr inbounds i32, i32 addrspace(4)* %in, i32 %tmp0
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362 %tmp2 = bitcast i32 addrspace(4)* %tmp1 to <16 x i32> addrspace(4)*
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363 %tmp3 = load <16 x i32>, <16 x i32> addrspace(4)* %tmp2, align 4
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364 store <16 x i32> %tmp3, <16 x i32> addrspace(1)* %out, align 32
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365 ret void
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366 }
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367
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368 ; GCN-LABEL: {{^}}s_load_imm_v16i32_salu_user:
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369 ; GCN-NOHSA: buffer_load_dwordx4
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370 ; GCN-NOHSA: buffer_load_dwordx4
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371 ; GCN-NOHSA: buffer_load_dwordx4
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372 ; GCN-NOHSA: buffer_load_dwordx4
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373 ; GCN-NOHSA: v_add_i32_e32
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parents:
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374 ; GCN-NOHSA: v_add_i32_e32
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parents:
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375 ; GCN-NOHSA: v_add_i32_e32
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parents:
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376 ; GCN-NOHSA: v_add_i32_e32
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parents:
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377 ; GCN-NOHSA: v_add_i32_e32
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parents:
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378 ; GCN-NOHSA: v_add_i32_e32
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parents:
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379 ; GCN-NOHSA: v_add_i32_e32
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parents:
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380 ; GCN-NOHSA: v_add_i32_e32
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parents:
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381 ; GCN-NOHSA: v_add_i32_e32
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parents:
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382 ; GCN-NOHSA: v_add_i32_e32
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parents:
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383 ; GCN-NOHSA: v_add_i32_e32
anatofuz
parents:
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384 ; GCN-NOHSA: v_add_i32_e32
anatofuz
parents:
diff changeset
385 ; GCN-NOHSA: v_add_i32_e32
anatofuz
parents:
diff changeset
386 ; GCN-NOHSA: v_add_i32_e32
anatofuz
parents:
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387 ; GCN-NOHSA: v_add_i32_e32
anatofuz
parents:
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388 ; GCN-NOHSA: buffer_store_dword
anatofuz
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389 ; GCN-HSA: flat_load_dwordx4
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390 ; GCN-HSA: flat_load_dwordx4
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parents:
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391 ; GCN-HSA: flat_load_dwordx4
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392 ; GCN-HSA: flat_load_dwordx4
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393 define amdgpu_kernel void @s_load_imm_v16i32_salu_user(i32 addrspace(1)* %out, i32 addrspace(4)* nocapture readonly %in) #1 {
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394 entry:
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395 %tmp0 = tail call i32 @llvm.amdgcn.workitem.id.x()
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396 %tmp1 = getelementptr inbounds i32, i32 addrspace(4)* %in, i32 %tmp0
anatofuz
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diff changeset
397 %tmp2 = bitcast i32 addrspace(4)* %tmp1 to <16 x i32> addrspace(4)*
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398 %tmp3 = load <16 x i32>, <16 x i32> addrspace(4)* %tmp2, align 4
anatofuz
parents:
diff changeset
399
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400 %elt0 = extractelement <16 x i32> %tmp3, i32 0
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parents:
diff changeset
401 %elt1 = extractelement <16 x i32> %tmp3, i32 1
anatofuz
parents:
diff changeset
402 %elt2 = extractelement <16 x i32> %tmp3, i32 2
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parents:
diff changeset
403 %elt3 = extractelement <16 x i32> %tmp3, i32 3
anatofuz
parents:
diff changeset
404 %elt4 = extractelement <16 x i32> %tmp3, i32 4
anatofuz
parents:
diff changeset
405 %elt5 = extractelement <16 x i32> %tmp3, i32 5
anatofuz
parents:
diff changeset
406 %elt6 = extractelement <16 x i32> %tmp3, i32 6
anatofuz
parents:
diff changeset
407 %elt7 = extractelement <16 x i32> %tmp3, i32 7
anatofuz
parents:
diff changeset
408 %elt8 = extractelement <16 x i32> %tmp3, i32 8
anatofuz
parents:
diff changeset
409 %elt9 = extractelement <16 x i32> %tmp3, i32 9
anatofuz
parents:
diff changeset
410 %elt10 = extractelement <16 x i32> %tmp3, i32 10
anatofuz
parents:
diff changeset
411 %elt11 = extractelement <16 x i32> %tmp3, i32 11
anatofuz
parents:
diff changeset
412 %elt12 = extractelement <16 x i32> %tmp3, i32 12
anatofuz
parents:
diff changeset
413 %elt13 = extractelement <16 x i32> %tmp3, i32 13
anatofuz
parents:
diff changeset
414 %elt14 = extractelement <16 x i32> %tmp3, i32 14
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parents:
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415 %elt15 = extractelement <16 x i32> %tmp3, i32 15
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parents:
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416
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parents:
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417 %add0 = add i32 %elt0, %elt1
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parents:
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418 %add1 = add i32 %add0, %elt2
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parents:
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419 %add2 = add i32 %add1, %elt3
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parents:
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420 %add3 = add i32 %add2, %elt4
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parents:
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421 %add4 = add i32 %add3, %elt5
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parents:
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422 %add5 = add i32 %add4, %elt6
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parents:
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423 %add6 = add i32 %add5, %elt7
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parents:
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424 %add7 = add i32 %add6, %elt8
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parents:
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425 %add8 = add i32 %add7, %elt9
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parents:
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426 %add9 = add i32 %add8, %elt10
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parents:
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427 %add10 = add i32 %add9, %elt11
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parents:
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428 %add11 = add i32 %add10, %elt12
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parents:
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429 %add12 = add i32 %add11, %elt13
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parents:
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430 %add13 = add i32 %add12, %elt14
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parents:
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431 %add14 = add i32 %add13, %elt15
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parents:
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432
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parents:
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433 store i32 %add14, i32 addrspace(1)* %out
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parents:
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434 ret void
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parents:
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435 }
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parents:
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436
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parents:
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437 ; Make sure we legalize vopc operands after moving an sopc to the value.
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parents:
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438
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parents:
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439 ; {{^}}sopc_vopc_legalize_bug:
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parents:
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440 ; GCN: s_load_dword [[SGPR:s[0-9]+]]
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parents:
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441 ; GCN: v_cmp_le_u32_e32 vcc, [[SGPR]], v{{[0-9]+}}
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parents:
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442 ; GCN: s_and_b64 vcc, exec, vcc
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parents:
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443 ; GCN: s_cbranch_vccnz [[EXIT:[A-Z0-9_]+]]
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parents:
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444 ; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
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parents:
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445 ; GCN-NOHSA: buffer_store_dword [[ONE]]
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parents:
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446 ; GCN-HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[ONE]]
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parents:
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447 ; GCN: {{^}}[[EXIT]]:
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parents:
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448 ; GCN: s_endpgm
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parents:
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449 define amdgpu_kernel void @sopc_vopc_legalize_bug(i32 %cond, i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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parents:
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450 bb3: ; preds = %bb2
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parents:
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451 %tmp0 = bitcast i32 %cond to float
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parents:
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452 %tmp1 = fadd float %tmp0, 2.500000e-01
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parents:
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453 %tmp2 = bitcast float %tmp1 to i32
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parents:
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454 %tmp3 = icmp ult i32 %tmp2, %cond
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parents:
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455 br i1 %tmp3, label %bb6, label %bb7
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parents:
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456
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parents:
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457 bb6:
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parents:
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458 store i32 1, i32 addrspace(1)* %out
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parents:
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459 br label %bb7
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parents:
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460
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parents:
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461 bb7: ; preds = %bb3
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parents:
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462 ret void
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parents:
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463 }
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parents:
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464
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parents:
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465 ; GCN-LABEL: {{^}}phi_visit_order:
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parents:
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466 ; GCN: v_add_i32_e64 v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 1, v{{[0-9]+}}
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parents:
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467 define amdgpu_kernel void @phi_visit_order() {
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parents:
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468 bb:
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parents:
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469 br label %bb1
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parents:
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470
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parents:
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471 bb1:
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parents:
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472 %tmp = phi i32 [ 0, %bb ], [ %tmp5, %bb4 ]
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parents:
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473 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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parents:
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474 %cnd = icmp eq i32 %tid, 0
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parents:
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475 br i1 %cnd, label %bb4, label %bb2
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parents:
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476
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parents:
diff changeset
477 bb2:
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parents:
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478 %tmp3 = add nsw i32 %tmp, 1
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parents:
diff changeset
479 br label %bb4
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parents:
diff changeset
480
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parents:
diff changeset
481 bb4:
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parents:
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482 %tmp5 = phi i32 [ %tmp3, %bb2 ], [ %tmp, %bb1 ]
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parents:
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483 store volatile i32 %tmp5, i32 addrspace(1)* undef
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parents:
diff changeset
484 br label %bb1
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parents:
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485 }
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parents:
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486
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parents:
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487 ; GCN-LABEL: {{^}}phi_imm_in_sgprs
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parents:
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488 ; GCN: s_movk_i32 [[A:s[0-9]+]], 0x400
anatofuz
parents:
diff changeset
489 ; GCN: s_movk_i32 [[B:s[0-9]+]], 0x400
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parents:
diff changeset
490 ; GCN: [[LOOP_LABEL:[0-9a-zA-Z_]+]]:
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parents:
diff changeset
491 ; GCN: s_xor_b32 [[B]], [[B]], [[A]]
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parents:
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492 ; GCN: s_cbranch_scc{{[01]}} [[LOOP_LABEL]]
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parents:
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493 define amdgpu_kernel void @phi_imm_in_sgprs(i32 addrspace(3)* %out, i32 %cond) {
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parents:
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494 entry:
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parents:
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495 br label %loop
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parents:
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496
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parents:
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497 loop:
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parents:
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498 %i = phi i32 [0, %entry], [%i.add, %loop]
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parents:
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499 %offset = phi i32 [1024, %entry], [%offset.xor, %loop]
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parents:
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500 %offset.xor = xor i32 %offset, 1024
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parents:
diff changeset
501 %offset.i = add i32 %offset.xor, %i
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parents:
diff changeset
502 %ptr = getelementptr i32, i32 addrspace(3)* %out, i32 %offset.i
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parents:
diff changeset
503 store i32 0, i32 addrspace(3)* %ptr
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parents:
diff changeset
504 %i.add = add i32 %i, 1
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parents:
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505 %cmp = icmp ult i32 %i.add, %cond
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parents:
diff changeset
506 br i1 %cmp, label %loop, label %exit
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parents:
diff changeset
507
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parents:
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508 exit:
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parents:
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509 ret void
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parents:
diff changeset
510 }
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parents:
diff changeset
511
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parents:
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512 attributes #0 = { nounwind readnone }
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parents:
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513 attributes #1 = { nounwind }