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221
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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck %s -check-prefixes=SI
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3 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -check-prefixes=VI
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4 ; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck %s -check-prefixes=EG
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150
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5
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6 declare i32 @llvm.amdgcn.workitem.id.x() #0
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7
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8 define amdgpu_kernel void @lshr_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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221
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9 ; SI-LABEL: lshr_i32:
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10 ; SI: ; %bb.0:
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11 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
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12 ; SI-NEXT: s_mov_b32 s3, 0xf000
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13 ; SI-NEXT: s_mov_b32 s2, -1
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14 ; SI-NEXT: s_waitcnt lgkmcnt(0)
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15 ; SI-NEXT: s_mov_b32 s0, s4
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16 ; SI-NEXT: s_mov_b32 s1, s5
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17 ; SI-NEXT: s_mov_b32 s4, s6
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18 ; SI-NEXT: s_mov_b32 s5, s7
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19 ; SI-NEXT: s_mov_b32 s6, s2
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20 ; SI-NEXT: s_mov_b32 s7, s3
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21 ; SI-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0
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22 ; SI-NEXT: s_waitcnt vmcnt(0)
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23 ; SI-NEXT: v_lshrrev_b32_e32 v0, v1, v0
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24 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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25 ; SI-NEXT: s_endpgm
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26 ;
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27 ; VI-LABEL: lshr_i32:
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28 ; VI: ; %bb.0:
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29 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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30 ; VI-NEXT: s_mov_b32 s7, 0xf000
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31 ; VI-NEXT: s_mov_b32 s6, -1
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32 ; VI-NEXT: s_waitcnt lgkmcnt(0)
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33 ; VI-NEXT: s_mov_b32 s4, s0
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34 ; VI-NEXT: s_mov_b32 s5, s1
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35 ; VI-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
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36 ; VI-NEXT: s_waitcnt lgkmcnt(0)
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37 ; VI-NEXT: s_lshr_b32 s0, s0, s1
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38 ; VI-NEXT: v_mov_b32_e32 v0, s0
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39 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
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40 ; VI-NEXT: s_endpgm
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41 ;
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42 ; EG-LABEL: lshr_i32:
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43 ; EG: ; %bb.0:
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44 ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
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45 ; EG-NEXT: TEX 0 @6
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46 ; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]
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47 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
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48 ; EG-NEXT: CF_END
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49 ; EG-NEXT: PAD
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50 ; EG-NEXT: Fetch clause starting at 6:
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51 ; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1
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52 ; EG-NEXT: ALU clause starting at 8:
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53 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
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54 ; EG-NEXT: ALU clause starting at 9:
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55 ; EG-NEXT: LSHR T0.X, T0.X, T0.Y,
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56 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
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57 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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150
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58 %b_ptr = getelementptr i32, i32 addrspace(1)* %in, i32 1
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59 %a = load i32, i32 addrspace(1)* %in
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60 %b = load i32, i32 addrspace(1)* %b_ptr
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61 %result = lshr i32 %a, %b
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62 store i32 %result, i32 addrspace(1)* %out
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63 ret void
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64 }
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65
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66 define amdgpu_kernel void @lshr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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221
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67 ; SI-LABEL: lshr_v2i32:
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68 ; SI: ; %bb.0:
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69 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
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70 ; SI-NEXT: s_mov_b32 s3, 0xf000
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71 ; SI-NEXT: s_mov_b32 s2, -1
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72 ; SI-NEXT: s_mov_b32 s10, s2
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73 ; SI-NEXT: s_mov_b32 s11, s3
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74 ; SI-NEXT: s_waitcnt lgkmcnt(0)
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75 ; SI-NEXT: s_mov_b32 s8, s6
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76 ; SI-NEXT: s_mov_b32 s9, s7
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77 ; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
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78 ; SI-NEXT: s_mov_b32 s0, s4
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79 ; SI-NEXT: s_mov_b32 s1, s5
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80 ; SI-NEXT: s_waitcnt vmcnt(0)
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81 ; SI-NEXT: v_lshr_b32_e32 v1, v1, v3
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82 ; SI-NEXT: v_lshr_b32_e32 v0, v0, v2
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83 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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84 ; SI-NEXT: s_endpgm
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85 ;
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86 ; VI-LABEL: lshr_v2i32:
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87 ; VI: ; %bb.0:
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88 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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89 ; VI-NEXT: s_mov_b32 s3, 0xf000
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90 ; VI-NEXT: s_mov_b32 s2, -1
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91 ; VI-NEXT: s_waitcnt lgkmcnt(0)
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92 ; VI-NEXT: s_load_dwordx2 s[8:9], s[6:7], 0x0
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93 ; VI-NEXT: s_load_dwordx2 s[6:7], s[6:7], 0x8
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94 ; VI-NEXT: s_mov_b32 s0, s4
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95 ; VI-NEXT: s_mov_b32 s1, s5
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96 ; VI-NEXT: s_waitcnt lgkmcnt(0)
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97 ; VI-NEXT: s_lshr_b32 s4, s9, s7
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98 ; VI-NEXT: s_lshr_b32 s5, s8, s6
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99 ; VI-NEXT: v_mov_b32_e32 v0, s5
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100 ; VI-NEXT: v_mov_b32_e32 v1, s4
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101 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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102 ; VI-NEXT: s_endpgm
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103 ;
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104 ; EG-LABEL: lshr_v2i32:
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105 ; EG: ; %bb.0:
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106 ; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
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107 ; EG-NEXT: TEX 1 @6
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108 ; EG-NEXT: ALU 3, @11, KC0[CB0:0-32], KC1[]
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109 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
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110 ; EG-NEXT: CF_END
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111 ; EG-NEXT: PAD
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112 ; EG-NEXT: Fetch clause starting at 6:
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113 ; EG-NEXT: VTX_READ_64 T1.XY, T0.X, 8, #1
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114 ; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1
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115 ; EG-NEXT: ALU clause starting at 10:
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116 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
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117 ; EG-NEXT: ALU clause starting at 11:
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118 ; EG-NEXT: LSHR * T0.Y, T0.Y, T1.Y,
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119 ; EG-NEXT: LSHR T0.X, T0.X, T1.X,
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120 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
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121 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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150
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122 %b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
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123 %a = load <2 x i32>, <2 x i32> addrspace(1)* %in
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124 %b = load <2 x i32>, <2 x i32> addrspace(1)* %b_ptr
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125 %result = lshr <2 x i32> %a, %b
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126 store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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127 ret void
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128 }
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129
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130 define amdgpu_kernel void @lshr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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221
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131 ; SI-LABEL: lshr_v4i32:
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132 ; SI: ; %bb.0:
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133 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
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134 ; SI-NEXT: s_mov_b32 s3, 0xf000
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135 ; SI-NEXT: s_mov_b32 s2, -1
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136 ; SI-NEXT: s_mov_b32 s10, s2
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137 ; SI-NEXT: s_mov_b32 s11, s3
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138 ; SI-NEXT: s_waitcnt lgkmcnt(0)
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139 ; SI-NEXT: s_mov_b32 s8, s6
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140 ; SI-NEXT: s_mov_b32 s9, s7
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141 ; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
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142 ; SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
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143 ; SI-NEXT: s_mov_b32 s0, s4
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144 ; SI-NEXT: s_mov_b32 s1, s5
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145 ; SI-NEXT: s_waitcnt vmcnt(0)
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146 ; SI-NEXT: v_lshr_b32_e32 v3, v3, v7
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147 ; SI-NEXT: v_lshr_b32_e32 v2, v2, v6
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148 ; SI-NEXT: v_lshr_b32_e32 v1, v1, v5
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149 ; SI-NEXT: v_lshr_b32_e32 v0, v0, v4
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150 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
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151 ; SI-NEXT: s_endpgm
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152 ;
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153 ; VI-LABEL: lshr_v4i32:
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154 ; VI: ; %bb.0:
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155 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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156 ; VI-NEXT: s_mov_b32 s3, 0xf000
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157 ; VI-NEXT: s_mov_b32 s2, -1
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158 ; VI-NEXT: s_waitcnt lgkmcnt(0)
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159 ; VI-NEXT: s_mov_b32 s0, s4
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160 ; VI-NEXT: s_mov_b32 s1, s5
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161 ; VI-NEXT: s_load_dwordx4 s[8:11], s[6:7], 0x0
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162 ; VI-NEXT: s_load_dwordx4 s[4:7], s[6:7], 0x10
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163 ; VI-NEXT: s_waitcnt lgkmcnt(0)
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164 ; VI-NEXT: s_lshr_b32 s7, s11, s7
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165 ; VI-NEXT: s_lshr_b32 s6, s10, s6
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166 ; VI-NEXT: s_lshr_b32 s5, s9, s5
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167 ; VI-NEXT: s_lshr_b32 s4, s8, s4
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168 ; VI-NEXT: v_mov_b32_e32 v0, s4
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169 ; VI-NEXT: v_mov_b32_e32 v1, s5
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170 ; VI-NEXT: v_mov_b32_e32 v2, s6
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171 ; VI-NEXT: v_mov_b32_e32 v3, s7
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172 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
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173 ; VI-NEXT: s_endpgm
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174 ;
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175 ; EG-LABEL: lshr_v4i32:
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176 ; EG: ; %bb.0:
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177 ; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
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178 ; EG-NEXT: TEX 1 @6
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179 ; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[]
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180 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
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181 ; EG-NEXT: CF_END
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182 ; EG-NEXT: PAD
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183 ; EG-NEXT: Fetch clause starting at 6:
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184 ; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1
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185 ; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
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186 ; EG-NEXT: ALU clause starting at 10:
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187 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
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188 ; EG-NEXT: ALU clause starting at 11:
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189 ; EG-NEXT: LSHR * T0.W, T0.W, T1.W,
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190 ; EG-NEXT: LSHR * T0.Z, T0.Z, T1.Z,
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191 ; EG-NEXT: LSHR * T0.Y, T0.Y, T1.Y,
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192 ; EG-NEXT: LSHR T0.X, T0.X, T1.X,
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193 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
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194 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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150
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195 %b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
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196 %a = load <4 x i32>, <4 x i32> addrspace(1)* %in
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197 %b = load <4 x i32>, <4 x i32> addrspace(1)* %b_ptr
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198 %result = lshr <4 x i32> %a, %b
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199 store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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200 ret void
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201 }
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202
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203 define amdgpu_kernel void @lshr_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
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221
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204 ; SI-LABEL: lshr_i64:
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205 ; SI: ; %bb.0:
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206 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
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207 ; SI-NEXT: s_mov_b32 s3, 0xf000
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208 ; SI-NEXT: s_mov_b32 s2, -1
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209 ; SI-NEXT: s_mov_b32 s10, s2
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210 ; SI-NEXT: s_mov_b32 s11, s3
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211 ; SI-NEXT: s_waitcnt lgkmcnt(0)
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212 ; SI-NEXT: s_mov_b32 s8, s6
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213 ; SI-NEXT: s_mov_b32 s9, s7
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214 ; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
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215 ; SI-NEXT: s_mov_b32 s0, s4
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216 ; SI-NEXT: s_mov_b32 s1, s5
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217 ; SI-NEXT: s_waitcnt vmcnt(0)
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218 ; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], v2
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219 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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220 ; SI-NEXT: s_endpgm
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221 ;
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222 ; VI-LABEL: lshr_i64:
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223 ; VI: ; %bb.0:
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224 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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225 ; VI-NEXT: s_mov_b32 s7, 0xf000
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226 ; VI-NEXT: s_mov_b32 s6, -1
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227 ; VI-NEXT: s_waitcnt lgkmcnt(0)
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228 ; VI-NEXT: s_mov_b32 s4, s0
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229 ; VI-NEXT: s_mov_b32 s5, s1
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230 ; VI-NEXT: s_load_dwordx4 s[0:3], s[2:3], 0x0
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231 ; VI-NEXT: s_waitcnt lgkmcnt(0)
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232 ; VI-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
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233 ; VI-NEXT: v_mov_b32_e32 v0, s0
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234 ; VI-NEXT: v_mov_b32_e32 v1, s1
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235 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
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236 ; VI-NEXT: s_endpgm
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237 ;
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238 ; EG-LABEL: lshr_i64:
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239 ; EG: ; %bb.0:
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240 ; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
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241 ; EG-NEXT: TEX 0 @6
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242 ; EG-NEXT: ALU 9, @9, KC0[CB0:0-32], KC1[]
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243 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
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244 ; EG-NEXT: CF_END
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245 ; EG-NEXT: PAD
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246 ; EG-NEXT: Fetch clause starting at 6:
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247 ; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
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248 ; EG-NEXT: ALU clause starting at 8:
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249 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
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250 ; EG-NEXT: ALU clause starting at 9:
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251 ; EG-NEXT: AND_INT * T0.W, T0.Z, literal.x,
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252 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
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253 ; EG-NEXT: LSHR T1.Z, T0.Y, PV.W,
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254 ; EG-NEXT: BIT_ALIGN_INT T0.W, T0.Y, T0.X, T0.Z,
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255 ; EG-NEXT: AND_INT * T1.W, T0.Z, literal.x,
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256 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
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257 ; EG-NEXT: CNDE_INT T0.X, PS, PV.W, PV.Z,
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258 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
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259 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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260 ; EG-NEXT: CNDE_INT * T0.Y, T1.W, T1.Z, 0.0,
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150
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261 %b_ptr = getelementptr i64, i64 addrspace(1)* %in, i64 1
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262 %a = load i64, i64 addrspace(1)* %in
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263 %b = load i64, i64 addrspace(1)* %b_ptr
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264 %result = lshr i64 %a, %b
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265 store i64 %result, i64 addrspace(1)* %out
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266 ret void
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267 }
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268
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269 define amdgpu_kernel void @lshr_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) {
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221
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270 ; SI-LABEL: lshr_v4i64:
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271 ; SI: ; %bb.0:
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272 ; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
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273 ; SI-NEXT: s_mov_b32 s3, 0xf000
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274 ; SI-NEXT: s_mov_b32 s2, -1
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275 ; SI-NEXT: s_mov_b32 s10, s2
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276 ; SI-NEXT: s_mov_b32 s11, s3
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277 ; SI-NEXT: s_waitcnt lgkmcnt(0)
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278 ; SI-NEXT: s_mov_b32 s8, s6
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279 ; SI-NEXT: s_mov_b32 s9, s7
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280 ; SI-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
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281 ; SI-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
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282 ; SI-NEXT: buffer_load_dwordx4 v[8:11], off, s[8:11], 0 offset:32
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283 ; SI-NEXT: buffer_load_dwordx4 v[11:14], off, s[8:11], 0 offset:48
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284 ; SI-NEXT: s_mov_b32 s0, s4
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285 ; SI-NEXT: s_mov_b32 s1, s5
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286 ; SI-NEXT: s_waitcnt vmcnt(1)
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287 ; SI-NEXT: v_lshr_b64 v[2:3], v[2:3], v10
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288 ; SI-NEXT: s_waitcnt vmcnt(0)
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289 ; SI-NEXT: v_lshr_b64 v[6:7], v[6:7], v13
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290 ; SI-NEXT: v_lshr_b64 v[4:5], v[4:5], v11
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291 ; SI-NEXT: v_lshr_b64 v[0:1], v[0:1], v8
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292 ; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
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293 ; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
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|
294 ; SI-NEXT: s_endpgm
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295 ;
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296 ; VI-LABEL: lshr_v4i64:
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297 ; VI: ; %bb.0:
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298 ; VI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24
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|
299 ; VI-NEXT: s_mov_b32 s19, 0xf000
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|
300 ; VI-NEXT: s_mov_b32 s18, -1
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|
|
301 ; VI-NEXT: s_waitcnt lgkmcnt(0)
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|
|
302 ; VI-NEXT: s_mov_b32 s16, s8
|
|
|
303 ; VI-NEXT: s_mov_b32 s17, s9
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|
|
304 ; VI-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
|
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|
305 ; VI-NEXT: s_load_dwordx8 s[8:15], s[10:11], 0x20
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|
|
306 ; VI-NEXT: s_waitcnt lgkmcnt(0)
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|
307 ; VI-NEXT: s_lshr_b64 s[6:7], s[6:7], s14
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|
|
308 ; VI-NEXT: s_lshr_b64 s[4:5], s[4:5], s12
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|
|
309 ; VI-NEXT: s_lshr_b64 s[2:3], s[2:3], s10
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|
310 ; VI-NEXT: s_lshr_b64 s[0:1], s[0:1], s8
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|
|
311 ; VI-NEXT: v_mov_b32_e32 v0, s4
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|
|
312 ; VI-NEXT: v_mov_b32_e32 v1, s5
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|
|
313 ; VI-NEXT: v_mov_b32_e32 v2, s6
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|
|
314 ; VI-NEXT: v_mov_b32_e32 v3, s7
|
|
|
315 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:16
|
|
|
316 ; VI-NEXT: s_nop 0
|
|
|
317 ; VI-NEXT: v_mov_b32_e32 v0, s0
|
|
|
318 ; VI-NEXT: v_mov_b32_e32 v1, s1
|
|
|
319 ; VI-NEXT: v_mov_b32_e32 v2, s2
|
|
|
320 ; VI-NEXT: v_mov_b32_e32 v3, s3
|
|
|
321 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0
|
|
|
322 ; VI-NEXT: s_endpgm
|
|
|
323 ;
|
|
|
324 ; EG-LABEL: lshr_v4i64:
|
|
|
325 ; EG: ; %bb.0:
|
|
|
326 ; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]
|
|
|
327 ; EG-NEXT: TEX 3 @6
|
|
|
328 ; EG-NEXT: ALU 34, @15, KC0[CB0:0-32], KC1[]
|
|
|
329 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T3.X, 0
|
|
|
330 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T0.X, 1
|
|
|
331 ; EG-NEXT: CF_END
|
|
|
332 ; EG-NEXT: Fetch clause starting at 6:
|
|
|
333 ; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 32, #1
|
|
|
334 ; EG-NEXT: VTX_READ_128 T2.XYZW, T0.X, 16, #1
|
|
|
335 ; EG-NEXT: VTX_READ_128 T3.XYZW, T0.X, 48, #1
|
|
|
336 ; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
|
|
|
337 ; EG-NEXT: ALU clause starting at 14:
|
|
|
338 ; EG-NEXT: MOV * T0.X, KC0[2].Z,
|
|
|
339 ; EG-NEXT: ALU clause starting at 15:
|
|
|
340 ; EG-NEXT: AND_INT * T1.W, T1.Z, literal.x,
|
|
|
341 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
|
|
|
342 ; EG-NEXT: LSHR T4.Z, T0.W, PV.W,
|
|
|
343 ; EG-NEXT: AND_INT T1.W, T1.Z, literal.x,
|
|
|
344 ; EG-NEXT: AND_INT * T3.W, T3.Z, literal.y,
|
|
|
345 ; EG-NEXT: 32(4.484155e-44), 31(4.344025e-44)
|
|
|
346 ; EG-NEXT: BIT_ALIGN_INT T4.X, T0.W, T0.Z, T1.Z,
|
|
|
347 ; EG-NEXT: LSHR T1.Y, T2.W, PS, BS:VEC_120/SCL_212
|
|
|
348 ; EG-NEXT: AND_INT * T0.Z, T3.Z, literal.x,
|
|
|
349 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
|
|
|
350 ; EG-NEXT: BIT_ALIGN_INT T0.W, T2.W, T2.Z, T3.Z,
|
|
|
351 ; EG-NEXT: AND_INT * T2.W, T3.X, literal.x,
|
|
|
352 ; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
|
|
|
353 ; EG-NEXT: AND_INT T5.X, T1.X, literal.x,
|
|
|
354 ; EG-NEXT: LSHR T3.Y, T2.Y, PS,
|
|
|
355 ; EG-NEXT: CNDE_INT T2.Z, T0.Z, PV.W, T1.Y,
|
|
|
356 ; EG-NEXT: BIT_ALIGN_INT T0.W, T2.Y, T2.X, T3.X,
|
|
|
357 ; EG-NEXT: AND_INT * T3.W, T3.X, literal.y,
|
|
|
358 ; EG-NEXT: 31(4.344025e-44), 32(4.484155e-44)
|
|
|
359 ; EG-NEXT: CNDE_INT T2.X, PS, PV.W, PV.Y,
|
|
|
360 ; EG-NEXT: LSHR T4.Y, T0.Y, PV.X,
|
|
|
361 ; EG-NEXT: CNDE_INT T1.Z, T1.W, T4.X, T4.Z,
|
|
|
362 ; EG-NEXT: BIT_ALIGN_INT T0.W, T0.Y, T0.X, T1.X, BS:VEC_102/SCL_221
|
|
|
363 ; EG-NEXT: AND_INT * T4.W, T1.X, literal.x,
|
|
|
364 ; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
|
|
|
365 ; EG-NEXT: CNDE_INT T1.X, PS, PV.W, PV.Y,
|
|
|
366 ; EG-NEXT: ADD_INT T0.W, KC0[2].Y, literal.x,
|
|
|
367 ; EG-NEXT: CNDE_INT * T2.W, T0.Z, T1.Y, 0.0,
|
|
|
368 ; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
|
|
|
369 ; EG-NEXT: LSHR T0.X, PV.W, literal.x,
|
|
|
370 ; EG-NEXT: CNDE_INT T2.Y, T3.W, T3.Y, 0.0,
|
|
|
371 ; EG-NEXT: CNDE_INT T1.W, T1.W, T4.Z, 0.0, BS:VEC_120/SCL_212
|
|
|
372 ; EG-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,
|
|
|
373 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
|
|
374 ; EG-NEXT: CNDE_INT * T1.Y, T4.W, T4.Y, 0.0,
|
|
150
|
375 %b_ptr = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i64 1
|
|
|
376 %a = load <4 x i64>, <4 x i64> addrspace(1)* %in
|
|
|
377 %b = load <4 x i64>, <4 x i64> addrspace(1)* %b_ptr
|
|
|
378 %result = lshr <4 x i64> %a, %b
|
|
|
379 store <4 x i64> %result, <4 x i64> addrspace(1)* %out
|
|
|
380 ret void
|
|
|
381 }
|
|
|
382
|
|
|
383 ; Make sure load width gets reduced to i32 load.
|
|
|
384 define amdgpu_kernel void @s_lshr_32_i64(i64 addrspace(1)* %out, [8 x i32], i64 %a) {
|
|
221
|
385 ; SI-LABEL: s_lshr_32_i64:
|
|
|
386 ; SI: ; %bb.0:
|
|
|
387 ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
|
|
388 ; SI-NEXT: s_load_dword s0, s[0:1], 0x14
|
|
|
389 ; SI-NEXT: s_mov_b32 s7, 0xf000
|
|
|
390 ; SI-NEXT: s_mov_b32 s6, -1
|
|
|
391 ; SI-NEXT: v_mov_b32_e32 v1, 0
|
|
|
392 ; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
393 ; SI-NEXT: v_mov_b32_e32 v0, s0
|
|
|
394 ; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
|
395 ; SI-NEXT: s_endpgm
|
|
|
396 ;
|
|
|
397 ; VI-LABEL: s_lshr_32_i64:
|
|
|
398 ; VI: ; %bb.0:
|
|
|
399 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
|
|
|
400 ; VI-NEXT: s_load_dword s0, s[0:1], 0x50
|
|
|
401 ; VI-NEXT: s_mov_b32 s7, 0xf000
|
|
|
402 ; VI-NEXT: s_mov_b32 s6, -1
|
|
|
403 ; VI-NEXT: v_mov_b32_e32 v1, 0
|
|
|
404 ; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
405 ; VI-NEXT: v_mov_b32_e32 v0, s0
|
|
|
406 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
|
407 ; VI-NEXT: s_endpgm
|
|
|
408 ;
|
|
|
409 ; EG-LABEL: s_lshr_32_i64:
|
|
|
410 ; EG: ; %bb.0:
|
|
|
411 ; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
|
|
|
412 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
|
|
|
413 ; EG-NEXT: CF_END
|
|
|
414 ; EG-NEXT: PAD
|
|
|
415 ; EG-NEXT: ALU clause starting at 4:
|
|
|
416 ; EG-NEXT: MOV T0.X, KC0[5].X,
|
|
|
417 ; EG-NEXT: MOV T0.Y, 0.0,
|
|
|
418 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
|
|
|
419 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
|
150
|
420 %result = lshr i64 %a, 32
|
|
|
421 store i64 %result, i64 addrspace(1)* %out
|
|
|
422 ret void
|
|
|
423 }
|
|
|
424
|
|
|
425 define amdgpu_kernel void @v_lshr_32_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) {
|
|
221
|
426 ; SI-LABEL: v_lshr_32_i64:
|
|
|
427 ; SI: ; %bb.0:
|
|
|
428 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
|
|
|
429 ; SI-NEXT: s_mov_b32 s6, 0
|
|
|
430 ; SI-NEXT: s_mov_b32 s7, 0xf000
|
|
|
431 ; SI-NEXT: v_mov_b32_e32 v1, 0
|
|
|
432 ; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
|
|
433 ; SI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
434 ; SI-NEXT: s_mov_b64 s[4:5], s[0:1]
|
|
|
435 ; SI-NEXT: s_mov_b64 s[0:1], s[2:3]
|
|
|
436 ; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
|
|
|
437 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 offset:4
|
|
|
438 ; SI-NEXT: v_mov_b32_e32 v3, v1
|
|
|
439 ; SI-NEXT: s_waitcnt vmcnt(0)
|
|
|
440 ; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
|
|
|
441 ; SI-NEXT: s_endpgm
|
|
|
442 ;
|
|
|
443 ; VI-LABEL: v_lshr_32_i64:
|
|
|
444 ; VI: ; %bb.0:
|
|
|
445 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
|
|
446 ; VI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
|
|
447 ; VI-NEXT: v_mov_b32_e32 v1, 0
|
|
|
448 ; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
449 ; VI-NEXT: v_mov_b32_e32 v2, s3
|
|
|
450 ; VI-NEXT: v_add_u32_e32 v4, vcc, s2, v0
|
|
|
451 ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v2, vcc
|
|
|
452 ; VI-NEXT: v_mov_b32_e32 v3, s1
|
|
|
453 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v0
|
|
|
454 ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
|
455 ; VI-NEXT: v_add_u32_e32 v4, vcc, 4, v4
|
|
|
456 ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
|
|
|
457 ; VI-NEXT: flat_load_dword v0, v[4:5]
|
|
|
458 ; VI-NEXT: s_waitcnt vmcnt(0)
|
|
|
459 ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
|
|
|
460 ; VI-NEXT: s_endpgm
|
|
|
461 ;
|
|
|
462 ; EG-LABEL: v_lshr_32_i64:
|
|
|
463 ; EG: ; %bb.0:
|
|
|
464 ; EG-NEXT: ALU 2, @8, KC0[CB0:0-32], KC1[]
|
|
|
465 ; EG-NEXT: TEX 0 @6
|
|
|
466 ; EG-NEXT: ALU 3, @11, KC0[CB0:0-32], KC1[]
|
|
|
467 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
|
|
|
468 ; EG-NEXT: CF_END
|
|
|
469 ; EG-NEXT: PAD
|
|
|
470 ; EG-NEXT: Fetch clause starting at 6:
|
|
|
471 ; EG-NEXT: VTX_READ_32 T0.X, T0.X, 4, #1
|
|
|
472 ; EG-NEXT: ALU clause starting at 8:
|
|
|
473 ; EG-NEXT: LSHL * T0.W, T0.X, literal.x,
|
|
|
474 ; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
|
|
|
475 ; EG-NEXT: ADD_INT * T0.X, KC0[2].Z, PV.W,
|
|
|
476 ; EG-NEXT: ALU clause starting at 11:
|
|
|
477 ; EG-NEXT: MOV T0.Y, 0.0,
|
|
|
478 ; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, T0.W,
|
|
|
479 ; EG-NEXT: LSHR * T1.X, PV.W, literal.x,
|
|
|
480 ; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
|
|
150
|
481 %tid = call i32 @llvm.amdgcn.workitem.id.x() #0
|
|
|
482 %gep.in = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
|
|
|
483 %gep.out = getelementptr i64, i64 addrspace(1)* %out, i32 %tid
|
|
|
484 %a = load i64, i64 addrspace(1)* %gep.in
|
|
|
485 %result = lshr i64 %a, 32
|
|
|
486 store i64 %result, i64 addrspace(1)* %gep.out
|
|
|
487 ret void
|
|
|
488 }
|
|
|
489
|
|
|
490 attributes #0 = { nounwind readnone }
|
