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221
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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=R600 %s
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3 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck --check-prefix=GFX6 %s
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4 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=GFX8 %s
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150
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5
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6 define amdgpu_kernel void @test_udivrem(i32 addrspace(1)* %out0, [8 x i32], i32 addrspace(1)* %out1, [8 x i32], i32 %x, [8 x i32], i32 %y) {
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221
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7 ; R600-LABEL: test_udivrem:
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8 ; R600: ; %bb.0:
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9 ; R600-NEXT: ALU 21, @4, KC0[CB0:0-32], KC1[]
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10 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.X, T3.X, 0
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11 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
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12 ; R600-NEXT: CF_END
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13 ; R600-NEXT: ALU clause starting at 4:
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14 ; R600-NEXT: SUB_INT T0.W, 0.0, KC0[9].X,
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15 ; R600-NEXT: RECIP_UINT * T0.X, KC0[9].X,
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16 ; R600-NEXT: MULLO_INT * T0.Y, PV.W, PS,
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17 ; R600-NEXT: MULHI * T0.Y, T0.X, PS,
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18 ; R600-NEXT: ADD_INT * T0.W, T0.X, PS,
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19 ; R600-NEXT: MULHI * T0.X, KC0[6].W, PV.W,
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20 ; R600-NEXT: MULLO_INT * T0.Y, PS, KC0[9].X,
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21 ; R600-NEXT: SUB_INT * T0.W, KC0[6].W, PS,
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22 ; R600-NEXT: SUB_INT T1.W, PV.W, KC0[9].X,
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23 ; R600-NEXT: SETGE_UINT * T2.W, PV.W, KC0[9].X,
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24 ; R600-NEXT: CNDE_INT * T0.W, PS, T0.W, PV.W,
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25 ; R600-NEXT: ADD_INT T0.Z, T0.X, 1,
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26 ; R600-NEXT: SUB_INT T1.W, PV.W, KC0[9].X,
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27 ; R600-NEXT: SETGE_UINT * T3.W, PV.W, KC0[9].X,
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28 ; R600-NEXT: CNDE_INT T1.X, PS, T0.W, PV.W,
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29 ; R600-NEXT: CNDE_INT T0.W, T2.W, T0.X, PV.Z,
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30 ; R600-NEXT: LSHR * T0.X, KC0[4].Z, literal.x,
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31 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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32 ; R600-NEXT: ADD_INT * T1.W, PV.W, 1,
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33 ; R600-NEXT: CNDE_INT T2.X, T3.W, T0.W, PV.W,
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34 ; R600-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,
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35 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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36 ;
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37 ; GFX6-LABEL: test_udivrem:
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38 ; GFX6: ; %bb.0:
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39 ; GFX6-NEXT: s_load_dword s3, s[0:1], 0x26
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40 ; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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41 ; GFX6-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x13
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42 ; GFX6-NEXT: s_load_dword s0, s[0:1], 0x1d
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43 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
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44 ; GFX6-NEXT: s_mov_b32 s6, -1
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45 ; GFX6-NEXT: s_mov_b32 s10, s6
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46 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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47 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s3
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48 ; GFX6-NEXT: s_sub_i32 s2, 0, s3
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49 ; GFX6-NEXT: s_mov_b32 s11, s7
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50 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
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51 ; GFX6-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
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52 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
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53 ; GFX6-NEXT: v_mul_lo_u32 v1, s2, v0
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54 ; GFX6-NEXT: v_mul_hi_u32 v1, v0, v1
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55 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v1, v0
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56 ; GFX6-NEXT: v_mul_hi_u32 v0, s0, v0
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57 ; GFX6-NEXT: v_mul_lo_u32 v1, v0, s3
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58 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
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59 ; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s0, v1
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60 ; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v1
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61 ; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
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62 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s3, v1
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63 ; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v2, s[0:1]
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64 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, 1, v0
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65 ; GFX6-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v1
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66 ; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1]
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67 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s3, v1
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68 ; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
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69 ; GFX6-NEXT: s_waitcnt expcnt(0)
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70 ; GFX6-NEXT: v_cndmask_b32_e64 v0, v1, v2, s[0:1]
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71 ; GFX6-NEXT: buffer_store_dword v0, off, s[8:11], 0
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72 ; GFX6-NEXT: s_endpgm
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73 ;
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74 ; GFX8-LABEL: test_udivrem:
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75 ; GFX8: ; %bb.0:
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76 ; GFX8-NEXT: s_load_dword s7, s[0:1], 0x98
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77 ; GFX8-NEXT: s_load_dword s6, s[0:1], 0x74
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78 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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79 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s7
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80 ; GFX8-NEXT: s_sub_i32 s2, 0, s7
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81 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
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82 ; GFX8-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0
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83 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
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84 ; GFX8-NEXT: v_mul_lo_u32 v1, s2, v0
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85 ; GFX8-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
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86 ; GFX8-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x4c
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87 ; GFX8-NEXT: v_mul_hi_u32 v1, v0, v1
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88 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v1, v0
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89 ; GFX8-NEXT: v_mul_hi_u32 v2, s6, v0
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90 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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91 ; GFX8-NEXT: v_mov_b32_e32 v0, s2
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92 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
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93 ; GFX8-NEXT: v_mul_lo_u32 v3, v2, s7
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94 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v2
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95 ; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s6, v3
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96 ; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s7, v3
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97 ; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1]
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98 ; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s7, v3
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99 ; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, v4, s[0:1]
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100 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, 1, v2
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101 ; GFX8-NEXT: v_cmp_le_u32_e64 s[0:1], s7, v3
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102 ; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, v4, s[0:1]
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103 ; GFX8-NEXT: flat_store_dword v[0:1], v2
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104 ; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s7, v3
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105 ; GFX8-NEXT: v_mov_b32_e32 v0, s4
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106 ; GFX8-NEXT: v_cndmask_b32_e64 v2, v3, v4, s[0:1]
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107 ; GFX8-NEXT: v_mov_b32_e32 v1, s5
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108 ; GFX8-NEXT: flat_store_dword v[0:1], v2
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109 ; GFX8-NEXT: s_endpgm
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150
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110 %result0 = udiv i32 %x, %y
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111 store i32 %result0, i32 addrspace(1)* %out0
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112 %result1 = urem i32 %x, %y
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113 store i32 %result1, i32 addrspace(1)* %out1
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114 ret void
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115 }
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116
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117 define amdgpu_kernel void @test_udivrem_v2(<2 x i32> addrspace(1)* %out, <2 x i32> %x, <2 x i32> %y) {
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221
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118 ; R600-LABEL: test_udivrem_v2:
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119 ; R600: ; %bb.0:
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120 ; R600-NEXT: ALU 29, @4, KC0[CB0:0-32], KC1[]
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121 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
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122 ; R600-NEXT: CF_END
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123 ; R600-NEXT: PAD
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124 ; R600-NEXT: ALU clause starting at 4:
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125 ; R600-NEXT: SUB_INT T0.W, 0.0, KC0[3].Z,
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126 ; R600-NEXT: RECIP_UINT * T0.X, KC0[3].Z,
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127 ; R600-NEXT: MULLO_INT * T0.Y, PV.W, PS,
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128 ; R600-NEXT: SUB_INT T0.W, 0.0, KC0[3].Y,
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129 ; R600-NEXT: RECIP_UINT * T0.Z, KC0[3].Y,
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130 ; R600-NEXT: MULLO_INT * T0.W, PV.W, PS,
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131 ; R600-NEXT: MULHI * T0.W, T0.Z, PS,
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132 ; R600-NEXT: ADD_INT T0.W, T0.Z, PS,
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133 ; R600-NEXT: MULHI * T0.Y, T0.X, T0.Y,
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134 ; R600-NEXT: ADD_INT T1.W, T0.X, PS,
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135 ; R600-NEXT: MULHI * T0.X, KC0[2].W, PV.W,
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136 ; R600-NEXT: MULHI * T0.Y, KC0[3].X, PV.W,
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137 ; R600-NEXT: MULLO_INT * T0.Y, PS, KC0[3].Z,
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138 ; R600-NEXT: SUB_INT T0.W, KC0[3].X, PS,
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139 ; R600-NEXT: MULLO_INT * T0.X, T0.X, KC0[3].Y,
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140 ; R600-NEXT: SUB_INT T0.Z, KC0[2].W, PS,
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141 ; R600-NEXT: SETGE_UINT T1.W, PV.W, KC0[3].Z,
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142 ; R600-NEXT: SUB_INT * T2.W, PV.W, KC0[3].Z,
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143 ; R600-NEXT: CNDE_INT T1.Z, PV.W, T0.W, PS,
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144 ; R600-NEXT: SETGE_UINT T0.W, PV.Z, KC0[3].Y,
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145 ; R600-NEXT: SUB_INT * T1.W, PV.Z, KC0[3].Y,
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146 ; R600-NEXT: CNDE_INT T0.Z, PV.W, T0.Z, PS,
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147 ; R600-NEXT: SETGE_UINT T0.W, PV.Z, KC0[3].Z,
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148 ; R600-NEXT: SUB_INT * T1.W, PV.Z, KC0[3].Z,
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149 ; R600-NEXT: CNDE_INT T0.Y, PV.W, T1.Z, PS,
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150 ; R600-NEXT: SETGE_UINT T0.W, PV.Z, KC0[3].Y,
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151 ; R600-NEXT: SUB_INT * T1.W, PV.Z, KC0[3].Y,
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152 ; R600-NEXT: CNDE_INT T0.X, PV.W, T0.Z, PS,
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153 ; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
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154 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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155 ;
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156 ; GFX6-LABEL: test_udivrem_v2:
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157 ; GFX6: ; %bb.0:
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158 ; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
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159 ; GFX6-NEXT: s_mov_b32 s2, 0x4f7ffffe
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160 ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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161 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
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162 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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163 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s6
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164 ; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s7
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165 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
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166 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
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167 ; GFX6-NEXT: v_mul_f32_e32 v0, s2, v0
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168 ; GFX6-NEXT: v_mul_f32_e32 v1, s2, v1
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169 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
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170 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
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171 ; GFX6-NEXT: s_sub_i32 s2, 0, s6
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172 ; GFX6-NEXT: v_mul_lo_u32 v2, s2, v0
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173 ; GFX6-NEXT: s_sub_i32 s2, 0, s7
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174 ; GFX6-NEXT: v_mul_lo_u32 v3, s2, v1
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175 ; GFX6-NEXT: s_mov_b32 s2, -1
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176 ; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
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177 ; GFX6-NEXT: v_mul_hi_u32 v3, v1, v3
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178 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0
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179 ; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
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180 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v3, v1
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181 ; GFX6-NEXT: v_mul_hi_u32 v1, s5, v1
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182 ; GFX6-NEXT: v_mul_lo_u32 v0, v0, s6
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183 ; GFX6-NEXT: v_mul_lo_u32 v1, v1, s7
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184 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
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185 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s6, v0
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186 ; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s5, v1
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187 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
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188 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
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189 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s6, v0
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190 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
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191 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
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192 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s7, v1
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193 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
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194 ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
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195 ; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s7, v1
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196 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
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197 ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
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198 ; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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199 ; GFX6-NEXT: s_endpgm
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200 ;
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201 ; GFX8-LABEL: test_udivrem_v2:
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202 ; GFX8: ; %bb.0:
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203 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
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204 ; GFX8-NEXT: s_mov_b32 s3, 0x4f7ffffe
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205 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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206 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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207 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s6
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208 ; GFX8-NEXT: s_sub_i32 s2, 0, s6
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209 ; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s7
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210 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
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211 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1
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212 ; GFX8-NEXT: v_mul_f32_e32 v0, s3, v0
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213 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
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214 ; GFX8-NEXT: v_mul_f32_e32 v1, s3, v1
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215 ; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
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216 ; GFX8-NEXT: v_mul_lo_u32 v2, s2, v0
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217 ; GFX8-NEXT: s_sub_i32 s2, 0, s7
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218 ; GFX8-NEXT: v_mul_hi_u32 v2, v0, v2
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219 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v2, v0
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220 ; GFX8-NEXT: v_mul_hi_u32 v0, s4, v0
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221 ; GFX8-NEXT: v_mul_lo_u32 v2, s2, v1
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222 ; GFX8-NEXT: v_mul_lo_u32 v0, v0, s6
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223 ; GFX8-NEXT: v_mul_hi_u32 v2, v1, v2
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224 ; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s4, v0
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225 ; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, s6, v0
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226 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
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227 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
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228 ; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, s6, v0
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229 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s6, v0
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230 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
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231 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, v2, v1
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232 ; GFX8-NEXT: v_mul_hi_u32 v1, s5, v1
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233 ; GFX8-NEXT: v_mul_lo_u32 v1, v1, s7
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234 ; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s5, v1
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235 ; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s7, v1
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236 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
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237 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
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238 ; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s7, v1
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239 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s7, v1
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240 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc
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241 ; GFX8-NEXT: v_mov_b32_e32 v3, s1
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242 ; GFX8-NEXT: v_mov_b32_e32 v2, s0
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243 ; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
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244 ; GFX8-NEXT: s_endpgm
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150
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245 %result0 = udiv <2 x i32> %x, %y
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246 store <2 x i32> %result0, <2 x i32> addrspace(1)* %out
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247 %result1 = urem <2 x i32> %x, %y
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248 store <2 x i32> %result1, <2 x i32> addrspace(1)* %out
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249 ret void
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250 }
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251
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252 define amdgpu_kernel void @test_udivrem_v4(<4 x i32> addrspace(1)* %out, <4 x i32> %x, <4 x i32> %y) {
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221
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253 ; R600-LABEL: test_udivrem_v4:
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254 ; R600: ; %bb.0:
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255 ; R600-NEXT: ALU 57, @4, KC0[CB0:0-32], KC1[]
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256 ; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T0.X, 1
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257 ; R600-NEXT: CF_END
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258 ; R600-NEXT: PAD
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259 ; R600-NEXT: ALU clause starting at 4:
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260 ; R600-NEXT: SUB_INT T0.W, 0.0, KC0[5].X,
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261 ; R600-NEXT: RECIP_UINT * T0.X, KC0[5].X,
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262 ; R600-NEXT: MULLO_INT * T0.Y, PV.W, PS,
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263 ; R600-NEXT: SUB_INT T0.W, 0.0, KC0[4].Z,
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264 ; R600-NEXT: RECIP_UINT * T0.Z, KC0[4].Z,
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265 ; R600-NEXT: MULLO_INT * T0.W, PV.W, PS,
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266 ; R600-NEXT: MULHI * T0.W, T0.Z, PS,
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267 ; R600-NEXT: ADD_INT T0.W, T0.Z, PS,
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268 ; R600-NEXT: MULHI * T0.Y, T0.X, T0.Y,
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269 ; R600-NEXT: ADD_INT T1.W, T0.X, PS,
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270 ; R600-NEXT: MULHI * T0.X, KC0[3].Z, PV.W,
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271 ; R600-NEXT: MULHI * T0.Y, KC0[4].X, PV.W,
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272 ; R600-NEXT: MULLO_INT * T0.Y, PS, KC0[5].X,
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273 ; R600-NEXT: RECIP_UINT * T0.Z, KC0[4].Y,
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274 ; R600-NEXT: SUB_INT T0.W, 0.0, KC0[4].W,
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275 ; R600-NEXT: RECIP_UINT * T1.X, KC0[4].W,
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276 ; R600-NEXT: MULLO_INT * T0.W, PV.W, PS,
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277 ; R600-NEXT: SUB_INT T1.W, 0.0, KC0[4].Y,
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278 ; R600-NEXT: MULHI * T0.W, T1.X, PS,
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279 ; R600-NEXT: ADD_INT T0.W, T1.X, PS,
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280 ; R600-NEXT: MULLO_INT * T1.X, PV.W, T0.Z,
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281 ; R600-NEXT: MULHI * T0.W, KC0[3].W, PV.W,
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282 ; R600-NEXT: MULLO_INT * T0.W, PS, KC0[4].W,
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283 ; R600-NEXT: SUB_INT T0.W, KC0[3].W, PS,
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284 ; R600-NEXT: MULHI * T1.X, T0.Z, T1.X,
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285 ; R600-NEXT: SETGE_UINT T1.Y, PV.W, KC0[4].W,
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286 ; R600-NEXT: ADD_INT T0.Z, T0.Z, PS,
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287 ; R600-NEXT: SUB_INT T1.W, KC0[4].X, T0.Y,
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288 ; R600-NEXT: MULLO_INT * T0.X, T0.X, KC0[4].Z,
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289 ; R600-NEXT: SUB_INT T0.Y, KC0[3].Z, PS,
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290 ; R600-NEXT: SETGE_UINT T1.Z, PV.W, KC0[5].X,
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291 ; R600-NEXT: SUB_INT * T2.W, PV.W, KC0[5].X,
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292 ; R600-NEXT: MULHI * T0.X, KC0[3].Y, T0.Z,
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293 ; R600-NEXT: SUB_INT T1.X, T0.W, KC0[4].W,
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294 ; R600-NEXT: CNDE_INT T2.Y, T1.Z, T1.W, T2.W,
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295 ; R600-NEXT: SETGE_UINT T0.Z, T0.Y, KC0[4].Z,
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296 ; R600-NEXT: SUB_INT T1.W, T0.Y, KC0[4].Z,
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297 ; R600-NEXT: MULLO_INT * T0.X, PS, KC0[4].Y,
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298 ; R600-NEXT: CNDE_INT T2.X, PV.Z, T0.Y, PV.W,
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299 ; R600-NEXT: SETGE_UINT T0.Y, PV.Y, KC0[5].X,
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300 ; R600-NEXT: SUB_INT T0.Z, PV.Y, KC0[5].X,
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301 ; R600-NEXT: SUB_INT T1.W, KC0[3].Y, PS,
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302 ; R600-NEXT: CNDE_INT * T0.W, T1.Y, T0.W, PV.X,
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|
303 ; R600-NEXT: SETGE_UINT T0.X, PS, KC0[4].W,
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304 ; R600-NEXT: SUB_INT T1.Y, PS, KC0[4].W,
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305 ; R600-NEXT: SETGE_UINT T1.Z, PV.W, KC0[4].Y,
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306 ; R600-NEXT: SUB_INT T2.W, PV.W, KC0[4].Y,
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307 ; R600-NEXT: CNDE_INT * T3.W, PV.Y, T2.Y, PV.Z,
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308 ; R600-NEXT: CNDE_INT T0.Y, PV.Z, T1.W, PV.W,
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|
309 ; R600-NEXT: CNDE_INT T3.Z, PV.X, T0.W, PV.Y, BS:VEC_021/SCL_122
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310 ; R600-NEXT: SETGE_UINT T0.W, T2.X, KC0[4].Z,
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|
|
311 ; R600-NEXT: SUB_INT * T1.W, T2.X, KC0[4].Z,
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|
|
312 ; R600-NEXT: CNDE_INT T3.Y, PV.W, T2.X, PS,
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|
|
313 ; R600-NEXT: SETGE_UINT T0.W, PV.Y, KC0[4].Y,
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314 ; R600-NEXT: SUB_INT * T1.W, PV.Y, KC0[4].Y,
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|
|
315 ; R600-NEXT: CNDE_INT T3.X, PV.W, T0.Y, PS,
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|
316 ; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
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|
|
317 ; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
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|
318 ;
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|
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319 ; GFX6-LABEL: test_udivrem_v4:
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320 ; GFX6: ; %bb.0:
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|
|
321 ; GFX6-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd
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322 ; GFX6-NEXT: s_mov_b32 s13, 0x4f7ffffe
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323 ; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
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|
|
324 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
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325 ; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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|
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326 ; GFX6-NEXT: v_cvt_f32_u32_e32 v0, s8
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|
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327 ; GFX6-NEXT: v_cvt_f32_u32_e32 v1, s9
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|
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328 ; GFX6-NEXT: s_sub_i32 s2, 0, s8
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329 ; GFX6-NEXT: s_sub_i32 s12, 0, s9
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330 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v0, v0
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|
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331 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v1, v1
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|
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332 ; GFX6-NEXT: v_cvt_f32_u32_e32 v3, s10
|
|
|
333 ; GFX6-NEXT: v_cvt_f32_u32_e32 v5, s11
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|
|
334 ; GFX6-NEXT: v_mul_f32_e32 v0, s13, v0
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|
|
335 ; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
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|
|
336 ; GFX6-NEXT: v_mul_f32_e32 v1, s13, v1
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|
|
337 ; GFX6-NEXT: v_cvt_u32_f32_e32 v1, v1
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|
|
338 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v3, v3
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|
|
339 ; GFX6-NEXT: v_mul_lo_u32 v2, s2, v0
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|
|
340 ; GFX6-NEXT: s_mov_b32 s2, -1
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|
|
341 ; GFX6-NEXT: v_mul_lo_u32 v4, s12, v1
|
|
|
342 ; GFX6-NEXT: v_mul_hi_u32 v2, v0, v2
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|
|
343 ; GFX6-NEXT: v_mul_hi_u32 v4, v1, v4
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|
|
344 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v2, v0
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|
|
345 ; GFX6-NEXT: v_mul_hi_u32 v0, s4, v0
|
|
|
346 ; GFX6-NEXT: v_add_i32_e32 v1, vcc, v4, v1
|
|
|
347 ; GFX6-NEXT: v_mul_hi_u32 v1, s5, v1
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|
|
348 ; GFX6-NEXT: v_mul_f32_e32 v2, s13, v3
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|
|
349 ; GFX6-NEXT: v_mul_lo_u32 v0, v0, s8
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|
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350 ; GFX6-NEXT: v_cvt_u32_f32_e32 v2, v2
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|
|
351 ; GFX6-NEXT: v_mul_lo_u32 v1, v1, s9
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|
|
352 ; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s4, v0
|
|
|
353 ; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s8, v0
|
|
|
354 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
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|
|
355 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
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|
|
356 ; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s8, v0
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|
|
357 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
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|
|
358 ; GFX6-NEXT: s_sub_i32 s4, 0, s10
|
|
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359 ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
|
|
|
360 ; GFX6-NEXT: v_mul_lo_u32 v3, s4, v2
|
|
|
361 ; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s5, v1
|
|
|
362 ; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s9, v1
|
|
|
363 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
|
|
|
364 ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
|
|
|
365 ; GFX6-NEXT: v_mul_hi_u32 v3, v2, v3
|
|
|
366 ; GFX6-NEXT: v_rcp_iflag_f32_e32 v4, v5
|
|
|
367 ; GFX6-NEXT: s_sub_i32 s4, 0, s11
|
|
|
368 ; GFX6-NEXT: v_add_i32_e32 v2, vcc, v3, v2
|
|
|
369 ; GFX6-NEXT: v_mul_f32_e32 v3, s13, v4
|
|
|
370 ; GFX6-NEXT: v_cvt_u32_f32_e32 v3, v3
|
|
|
371 ; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s9, v1
|
|
|
372 ; GFX6-NEXT: v_mul_hi_u32 v2, s6, v2
|
|
|
373 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
|
|
|
374 ; GFX6-NEXT: v_mul_lo_u32 v5, s4, v3
|
|
|
375 ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc
|
|
|
376 ; GFX6-NEXT: v_mul_lo_u32 v2, v2, s10
|
|
|
377 ; GFX6-NEXT: v_mul_hi_u32 v4, v3, v5
|
|
|
378 ; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s6, v2
|
|
|
379 ; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s10, v2
|
|
|
380 ; GFX6-NEXT: v_add_i32_e32 v3, vcc, v4, v3
|
|
|
381 ; GFX6-NEXT: v_mul_hi_u32 v3, s7, v3
|
|
|
382 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s10, v2
|
|
|
383 ; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
|
|
|
384 ; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s10, v2
|
|
|
385 ; GFX6-NEXT: v_mul_lo_u32 v3, v3, s11
|
|
|
386 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s10, v2
|
|
|
387 ; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc
|
|
|
388 ; GFX6-NEXT: v_sub_i32_e32 v3, vcc, s7, v3
|
|
|
389 ; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s11, v3
|
|
|
390 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s11, v3
|
|
|
391 ; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
|
|
|
392 ; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s11, v3
|
|
|
393 ; GFX6-NEXT: v_cmp_le_u32_e32 vcc, s11, v3
|
|
|
394 ; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
|
|
|
395 ; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
|
|
396 ; GFX6-NEXT: s_endpgm
|
|
|
397 ;
|
|
|
398 ; GFX8-LABEL: test_udivrem_v4:
|
|
|
399 ; GFX8: ; %bb.0:
|
|
|
400 ; GFX8-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x34
|
|
|
401 ; GFX8-NEXT: s_mov_b32 s12, 0x4f7ffffe
|
|
|
402 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
|
|
|
403 ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
404 ; GFX8-NEXT: v_cvt_f32_u32_e32 v0, s8
|
|
|
405 ; GFX8-NEXT: s_sub_i32 s2, 0, s8
|
|
|
406 ; GFX8-NEXT: v_cvt_f32_u32_e32 v1, s9
|
|
|
407 ; GFX8-NEXT: v_cvt_f32_u32_e32 v4, s11
|
|
|
408 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v0, v0
|
|
|
409 ; GFX8-NEXT: s_sub_i32 s3, 0, s9
|
|
|
410 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v1, v1
|
|
|
411 ; GFX8-NEXT: v_cvt_f32_u32_e32 v2, s10
|
|
|
412 ; GFX8-NEXT: v_mul_f32_e32 v0, s12, v0
|
|
|
413 ; GFX8-NEXT: v_cvt_u32_f32_e32 v0, v0
|
|
|
414 ; GFX8-NEXT: v_mul_f32_e32 v1, s12, v1
|
|
|
415 ; GFX8-NEXT: v_cvt_u32_f32_e32 v1, v1
|
|
|
416 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v2, v2
|
|
|
417 ; GFX8-NEXT: v_mul_lo_u32 v3, s2, v0
|
|
|
418 ; GFX8-NEXT: s_sub_i32 s2, 0, s10
|
|
|
419 ; GFX8-NEXT: v_mul_f32_e32 v2, s12, v2
|
|
|
420 ; GFX8-NEXT: v_mul_hi_u32 v3, v0, v3
|
|
|
421 ; GFX8-NEXT: v_cvt_u32_f32_e32 v2, v2
|
|
|
422 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v3, v0
|
|
|
423 ; GFX8-NEXT: v_mul_hi_u32 v0, s4, v0
|
|
|
424 ; GFX8-NEXT: v_rcp_iflag_f32_e32 v3, v4
|
|
|
425 ; GFX8-NEXT: v_mul_lo_u32 v4, s3, v1
|
|
|
426 ; GFX8-NEXT: v_mul_lo_u32 v0, v0, s8
|
|
|
427 ; GFX8-NEXT: v_mul_f32_e32 v3, s12, v3
|
|
|
428 ; GFX8-NEXT: v_mul_hi_u32 v4, v1, v4
|
|
|
429 ; GFX8-NEXT: v_cvt_u32_f32_e32 v3, v3
|
|
|
430 ; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s4, v0
|
|
|
431 ; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s8, v0
|
|
|
432 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
|
|
|
433 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
|
|
|
434 ; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s8, v0
|
|
|
435 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s8, v0
|
|
|
436 ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc
|
|
|
437 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, v4, v1
|
|
|
438 ; GFX8-NEXT: v_mul_hi_u32 v1, s5, v1
|
|
|
439 ; GFX8-NEXT: v_mul_lo_u32 v4, s2, v2
|
|
|
440 ; GFX8-NEXT: s_sub_i32 s2, 0, s11
|
|
|
441 ; GFX8-NEXT: v_mul_lo_u32 v1, v1, s9
|
|
|
442 ; GFX8-NEXT: v_mul_hi_u32 v4, v2, v4
|
|
|
443 ; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s5, v1
|
|
|
444 ; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s9, v1
|
|
|
445 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
|
|
|
446 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
|
|
|
447 ; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s9, v1
|
|
|
448 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s9, v1
|
|
|
449 ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc
|
|
|
450 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, v4, v2
|
|
|
451 ; GFX8-NEXT: v_mul_hi_u32 v2, s6, v2
|
|
|
452 ; GFX8-NEXT: v_mul_lo_u32 v4, s2, v3
|
|
|
453 ; GFX8-NEXT: v_mul_lo_u32 v2, v2, s10
|
|
|
454 ; GFX8-NEXT: v_mul_hi_u32 v4, v3, v4
|
|
|
455 ; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s6, v2
|
|
|
456 ; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s10, v2
|
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457 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s10, v2
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458 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
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459 ; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s10, v2
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460 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s10, v2
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461 ; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc
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462 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, v4, v3
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463 ; GFX8-NEXT: v_mul_hi_u32 v3, s7, v3
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464 ; GFX8-NEXT: v_mul_lo_u32 v3, v3, s11
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465 ; GFX8-NEXT: v_sub_u32_e32 v3, vcc, s7, v3
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466 ; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s11, v3
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467 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s11, v3
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468 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
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469 ; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s11, v3
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470 ; GFX8-NEXT: v_cmp_le_u32_e32 vcc, s11, v3
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471 ; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v4, vcc
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472 ; GFX8-NEXT: v_mov_b32_e32 v5, s1
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473 ; GFX8-NEXT: v_mov_b32_e32 v4, s0
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474 ; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
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475 ; GFX8-NEXT: s_endpgm
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150
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476 %result0 = udiv <4 x i32> %x, %y
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477 store <4 x i32> %result0, <4 x i32> addrspace(1)* %out
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478 %result1 = urem <4 x i32> %x, %y
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479 store <4 x i32> %result1, <4 x i32> addrspace(1)* %out
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480 ret void
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481 }
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