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1 ; RUN: llc -march=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
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2 ; RUN: llc -march=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
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3 ; RUN: llc -march=amdgcn -mcpu=gfx801 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
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4 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
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5 ; RUN: llc -march=amdgcn -mcpu=gfx906 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN-DL %s
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150
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6
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7 ; GCN-LABEL: {{^}}scalar_xnor_i32_one_use
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8 ; GCN: s_xnor_b32
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9 define amdgpu_kernel void @scalar_xnor_i32_one_use(
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10 i32 addrspace(1)* %r0, i32 %a, i32 %b) {
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11 entry:
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12 %xor = xor i32 %a, %b
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13 %r0.val = xor i32 %xor, -1
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14 store i32 %r0.val, i32 addrspace(1)* %r0
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15 ret void
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16 }
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17
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18 ; GCN-LABEL: {{^}}scalar_xnor_i32_mul_use
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19 ; GCN-NOT: s_xnor_b32
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20 ; GCN: s_xor_b32
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21 ; GCN: s_not_b32
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22 ; GCN: s_add_i32
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23 define amdgpu_kernel void @scalar_xnor_i32_mul_use(
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24 i32 addrspace(1)* %r0, i32 addrspace(1)* %r1, i32 %a, i32 %b) {
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25 entry:
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26 %xor = xor i32 %a, %b
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27 %r0.val = xor i32 %xor, -1
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28 %r1.val = add i32 %xor, %a
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29 store i32 %r0.val, i32 addrspace(1)* %r0
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30 store i32 %r1.val, i32 addrspace(1)* %r1
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31 ret void
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32 }
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33
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34 ; GCN-LABEL: {{^}}scalar_xnor_i64_one_use
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35 ; GCN: s_xnor_b64
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36 define amdgpu_kernel void @scalar_xnor_i64_one_use(
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37 i64 addrspace(1)* %r0, i64 %a, i64 %b) {
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38 entry:
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39 %xor = xor i64 %a, %b
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40 %r0.val = xor i64 %xor, -1
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41 store i64 %r0.val, i64 addrspace(1)* %r0
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42 ret void
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43 }
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44
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45 ; GCN-LABEL: {{^}}scalar_xnor_i64_mul_use
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46 ; GCN-NOT: s_xnor_b64
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47 ; GCN: s_xor_b64
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48 ; GCN: s_not_b64
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49 ; GCN: s_add_u32
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50 ; GCN: s_addc_u32
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51 define amdgpu_kernel void @scalar_xnor_i64_mul_use(
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52 i64 addrspace(1)* %r0, i64 addrspace(1)* %r1, i64 %a, i64 %b) {
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53 entry:
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54 %xor = xor i64 %a, %b
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55 %r0.val = xor i64 %xor, -1
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56 %r1.val = add i64 %xor, %a
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57 store i64 %r0.val, i64 addrspace(1)* %r0
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58 store i64 %r1.val, i64 addrspace(1)* %r1
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59 ret void
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60 }
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61
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62 ; GCN-LABEL: {{^}}vector_xnor_i32_one_use
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63 ; GCN-NOT: s_xnor_b32
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64 ; GCN: v_not_b32
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65 ; GCN: v_xor_b32
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66 ; GCN-DL: v_xnor_b32
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67 define i32 @vector_xnor_i32_one_use(i32 %a, i32 %b) {
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68 entry:
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69 %xor = xor i32 %a, %b
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70 %r = xor i32 %xor, -1
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71 ret i32 %r
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72 }
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73
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74 ; GCN-LABEL: {{^}}vector_xnor_i64_one_use
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75 ; GCN-NOT: s_xnor_b64
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76 ; GCN: v_not_b32
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77 ; GCN: v_not_b32
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78 ; GCN: v_xor_b32
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79 ; GCN: v_xor_b32
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80 ; GCN-DL: v_xnor_b32
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81 ; GCN-DL: v_xnor_b32
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82 define i64 @vector_xnor_i64_one_use(i64 %a, i64 %b) {
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83 entry:
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84 %xor = xor i64 %a, %b
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85 %r = xor i64 %xor, -1
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86 ret i64 %r
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87 }
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88
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89 ; GCN-LABEL: {{^}}xnor_s_v_i32_one_use
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90 ; GCN-NOT: s_xnor_b32
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91 ; GCN: s_not_b32
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92 ; GCN: v_xor_b32
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93 define amdgpu_kernel void @xnor_s_v_i32_one_use(i32 addrspace(1)* %out, i32 %s) {
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94 %v = call i32 @llvm.amdgcn.workitem.id.x() #1
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95 %xor = xor i32 %s, %v
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96 %d = xor i32 %xor, -1
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97 store i32 %d, i32 addrspace(1)* %out
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98 ret void
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99 }
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100
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101 ; GCN-LABEL: {{^}}xnor_v_s_i32_one_use
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102 ; GCN-NOT: s_xnor_b32
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103 ; GCN: s_not_b32
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104 ; GCN: v_xor_b32
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105 define amdgpu_kernel void @xnor_v_s_i32_one_use(i32 addrspace(1)* %out, i32 %s) {
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106 %v = call i32 @llvm.amdgcn.workitem.id.x() #1
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107 %xor = xor i32 %v, %s
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108 %d = xor i32 %xor, -1
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109 store i32 %d, i32 addrspace(1)* %out
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110 ret void
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111 }
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112
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113 ; GCN-LABEL: {{^}}xnor_i64_s_v_one_use
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114 ; GCN-NOT: s_xnor_b64
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115 ; GCN: s_not_b64
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116 ; GCN: v_xor_b32
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117 ; GCN: v_xor_b32
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118 ; GCN-DL: v_xnor_b32
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119 ; GCN-DL: v_xnor_b32
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120 define amdgpu_kernel void @xnor_i64_s_v_one_use(
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121 i64 addrspace(1)* %r0, i64 %a) {
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122 entry:
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123 %b32 = call i32 @llvm.amdgcn.workitem.id.x() #1
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124 %b64 = zext i32 %b32 to i64
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125 %b = shl i64 %b64, 29
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126 %xor = xor i64 %a, %b
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127 %r0.val = xor i64 %xor, -1
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128 store i64 %r0.val, i64 addrspace(1)* %r0
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129 ret void
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130 }
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131
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132 ; GCN-LABEL: {{^}}xnor_i64_v_s_one_use
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133 ; GCN-NOT: s_xnor_b64
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134 ; GCN: s_not_b64
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135 ; GCN: v_xor_b32
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136 ; GCN: v_xor_b32
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137 ; GCN-DL: v_xnor_b32
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138 ; GCN-DL: v_xnor_b32
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139 define amdgpu_kernel void @xnor_i64_v_s_one_use(
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140 i64 addrspace(1)* %r0, i64 %a) {
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141 entry:
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142 %b32 = call i32 @llvm.amdgcn.workitem.id.x() #1
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143 %b64 = zext i32 %b32 to i64
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144 %b = shl i64 %b64, 29
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145 %xor = xor i64 %b, %a
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146 %r0.val = xor i64 %xor, -1
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147 store i64 %r0.val, i64 addrspace(1)* %r0
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148 ret void
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149 }
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150
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151 ; GCN-LABEL: {{^}}vector_xor_na_b_i32_one_use
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152 ; GCN-NOT: s_xnor_b32
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153 ; GCN: v_not_b32
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154 ; GCN: v_xor_b32
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155 ; GCN-DL: v_xnor_b32
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156 define i32 @vector_xor_na_b_i32_one_use(i32 %a, i32 %b) {
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157 entry:
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158 %na = xor i32 %a, -1
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159 %r = xor i32 %na, %b
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160 ret i32 %r
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161 }
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162
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163 ; GCN-LABEL: {{^}}vector_xor_a_nb_i32_one_use
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164 ; GCN-NOT: s_xnor_b32
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165 ; GCN: v_not_b32
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166 ; GCN: v_xor_b32
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167 ; GCN-DL: v_xnor_b32
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168 define i32 @vector_xor_a_nb_i32_one_use(i32 %a, i32 %b) {
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169 entry:
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170 %nb = xor i32 %b, -1
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171 %r = xor i32 %a, %nb
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172 ret i32 %r
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173 }
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174
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175 ; GCN-LABEL: {{^}}scalar_xor_a_nb_i64_one_use
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176 ; GCN: s_xnor_b64
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177 define amdgpu_kernel void @scalar_xor_a_nb_i64_one_use(
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178 i64 addrspace(1)* %r0, i64 %a, i64 %b) {
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179 entry:
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180 %nb = xor i64 %b, -1
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181 %r0.val = xor i64 %a, %nb
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182 store i64 %r0.val, i64 addrspace(1)* %r0
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183 ret void
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184 }
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185
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186 ; GCN-LABEL: {{^}}scalar_xor_na_b_i64_one_use
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187 ; GCN: s_xnor_b64
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188 define amdgpu_kernel void @scalar_xor_na_b_i64_one_use(
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189 i64 addrspace(1)* %r0, i64 %a, i64 %b) {
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190 entry:
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191 %na = xor i64 %a, -1
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192 %r0.val = xor i64 %na, %b
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193 store i64 %r0.val, i64 addrspace(1)* %r0
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194 ret void
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195 }
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196
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197 ; Function Attrs: nounwind readnone
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198 declare i32 @llvm.amdgcn.workitem.id.x() #0
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