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annotate llvm/test/CodeGen/AMDGPU/zero_extend.ll @ 223:5f17cb93ff66 llvm-original

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LLVM13 (2021/7/18)
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Sun, 18 Jul 2021 22:43:00 +0900
parents 79ff65ed7e25
children c4bab56944e8
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79ff65ed7e25 LLVM12 Original
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
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1 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GCN %s
79ff65ed7e25 LLVM12 Original
Shinji KONO <kono@ie.u-ryukyu.ac.jp>
parents: 150
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2 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GCN %s
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3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 %s
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4
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5 ; R600: {{^}}s_mad_zext_i32_to_i64:
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6 ; R600: MEM_RAT_CACHELESS STORE_RAW
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7 ; R600: MEM_RAT_CACHELESS STORE_RAW
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8
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9 ; GCN: {{^}}s_mad_zext_i32_to_i64:
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10 ; GCN: v_mov_b32_e32 v[[V_ZERO:[0-9]]], 0{{$}}
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11 ; GCN: buffer_store_dwordx2 v[0:[[V_ZERO]]{{\]}}
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12 define amdgpu_kernel void @s_mad_zext_i32_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) #0 {
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13 entry:
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14 %tmp0 = mul i32 %a, %b
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15 %tmp1 = add i32 %tmp0, %c
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16 %tmp2 = zext i32 %tmp1 to i64
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17 store i64 %tmp2, i64 addrspace(1)* %out
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18 ret void
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19 }
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20
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21 ; GCN-LABEL: {{^}}s_cmp_zext_i1_to_i32
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22 ; GCN: v_cndmask_b32
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23 define amdgpu_kernel void @s_cmp_zext_i1_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
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24 entry:
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25 %tmp0 = icmp eq i32 %a, %b
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26 %tmp1 = zext i1 %tmp0 to i32
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27 store i32 %tmp1, i32 addrspace(1)* %out
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28 ret void
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29 }
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30
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31 ; GCN-LABEL: {{^}}s_arg_zext_i1_to_i64:
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32 define amdgpu_kernel void @s_arg_zext_i1_to_i64(i64 addrspace(1)* %out, i1 zeroext %arg) #0 {
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33 %ext = zext i1 %arg to i64
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34 store i64 %ext, i64 addrspace(1)* %out, align 8
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35 ret void
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36 }
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37
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38 ; GCN-LABEL: {{^}}s_cmp_zext_i1_to_i64:
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39 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, 0
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40 ; GCN-DAG: v_cmp_eq_u32
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41 ; GCN: v_cndmask_b32
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42 define amdgpu_kernel void @s_cmp_zext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) #0 {
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43 %cmp = icmp eq i32 %a, %b
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44 %ext = zext i1 %cmp to i64
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45 store i64 %ext, i64 addrspace(1)* %out, align 8
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46 ret void
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47 }
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48
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49 ; FIXME: Why different commute?
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50 ; GCN-LABEL: {{^}}s_cmp_zext_i1_to_i16
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51 ; GCN: s_load_dword [[A:s[0-9]+]]
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52 ; GCN: s_load_dword [[B:s[0-9]+]]
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53
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54 ; GCN: s_mov_b32 [[MASK:s[0-9]+]], 0xffff{{$}}
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55 ; GCN-DAG: s_and_b32 [[MASK_A:s[0-9]+]], [[A]], [[MASK]]
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56 ; GCN-DAG: s_and_b32 [[MASK_B:s[0-9]+]], [[B]], [[MASK]]
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57 ; GCN: v_mov_b32_e32 [[V_B:v[0-9]+]], [[B]]
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58 ; GCN: v_cmp_eq_u32_e32 vcc, [[MASK_A]], [[V_B]]
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59
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60 ; GCN: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
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61 ; GCN: buffer_store_short [[RESULT]]
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62 define amdgpu_kernel void @s_cmp_zext_i1_to_i16(i16 addrspace(1)* %out, [8 x i32], i16 zeroext %a, [8 x i32], i16 zeroext %b) #0 {
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63 %tmp0 = icmp eq i16 %a, %b
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64 %tmp1 = zext i1 %tmp0 to i16
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65 store i16 %tmp1, i16 addrspace(1)* %out
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66 ret void
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67 }
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68
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69 attributes #0 = { nounwind }