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1 ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
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2 ; RUN: -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
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3 ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
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4 ; RUN: -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
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5 ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=GP32 \
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6 ; RUN: -check-prefix=R2 -check-prefix=R2-R6 -check-prefix=NOT-R6
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7 ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
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8 ; RUN: -check-prefix=GP32 -check-prefix=R6 -check-prefix=R2-R6
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9 ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
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10 ; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
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11 ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
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12 ; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
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13 ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
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14 ; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6
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15 ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
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16 ; RUN: -check-prefix=R2 -check-prefix=R2-R6 \
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17 ; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6
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18 ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
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19 ; RUN: -check-prefix=64R6 -check-prefix=R6 -check-prefix=R2-R6
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20
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21 define signext i1 @srem_i1(i1 signext %a, i1 signext %b) {
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22 entry:
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23 ; ALL-LABEL: srem_i1:
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24
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25 ; NOT-R6: div $zero, $4, $5
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26 ; NOT-R6: teq $5, $zero, 7
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27 ; NOT-R6: mfhi $[[T0:[0-9]+]]
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28 ; NOT-R6: sll $[[T1:[0-9]+]], $[[T0]], 31
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29 ; NOT-R6: sra $2, $[[T1]], 31
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30
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31 ; R6: mod $[[T0:[0-9]+]], $4, $5
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32 ; R6: teq $5, $zero, 7
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33 ; R6: sll $[[T3:[0-9]+]], $[[T0]], 31
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34 ; R6: sra $2, $[[T3]], 31
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35
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36 %r = srem i1 %a, %b
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37 ret i1 %r
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38 }
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39
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40 define signext i8 @srem_i8(i8 signext %a, i8 signext %b) {
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41 entry:
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42 ; ALL-LABEL: srem_i8:
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43
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44 ; NOT-R2-R6: div $zero, $4, $5
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45 ; NOT-R2-R6: teq $5, $zero, 7
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46 ; NOT-R2-R6: mfhi $[[T0:[0-9]+]]
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47 ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 24
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48 ; NOT-R2-R6: sra $2, $[[T1]], 24
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49
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50 ; R2: div $zero, $4, $5
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51 ; R2: teq $5, $zero, 7
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52 ; R2: mfhi $[[T0:[0-9]+]]
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53 ; R2: seb $2, $[[T0]]
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54
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55 ; R6: mod $[[T0:[0-9]+]], $4, $5
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56 ; R6: teq $5, $zero, 7
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57 ; R6: seb $2, $[[T0]]
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58
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59 %r = srem i8 %a, %b
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60 ret i8 %r
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61 }
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62
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63 define signext i16 @srem_i16(i16 signext %a, i16 signext %b) {
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64 entry:
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65 ; ALL-LABEL: srem_i16:
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66
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67 ; NOT-R2-R6: div $zero, $4, $5
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68 ; NOT-R2-R6: teq $5, $zero, 7
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69 ; NOT-R2-R6: mfhi $[[T0:[0-9]+]]
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70 ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 16
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71 ; NOT-R2-R6: sra $2, $[[T1]], 16
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72
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73 ; R2: div $zero, $4, $5
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74 ; R2: teq $5, $zero, 7
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75 ; R2: mfhi $[[T0:[0-9]+]]
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76 ; R2: seh $2, $[[T1]]
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77
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78 ; R6: mod $[[T0:[0-9]+]], $4, $5
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79 ; R6: teq $5, $zero, 7
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80 ; R6: seh $2, $[[T0]]
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81
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82 %r = srem i16 %a, %b
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83 ret i16 %r
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84 }
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85
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86 define signext i32 @srem_i32(i32 signext %a, i32 signext %b) {
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87 entry:
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88 ; ALL-LABEL: srem_i32:
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89
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90 ; NOT-R6: div $zero, $4, $5
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91 ; NOT-R6: teq $5, $zero, 7
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92 ; NOT-R6: mfhi $2
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93
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94 ; R6: mod $2, $4, $5
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95 ; R6: teq $5, $zero, 7
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96
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97 %r = srem i32 %a, %b
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98 ret i32 %r
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99 }
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100
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101 define signext i64 @srem_i64(i64 signext %a, i64 signext %b) {
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102 entry:
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103 ; ALL-LABEL: srem_i64:
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104
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105 ; GP32: lw $25, %call16(__moddi3)($gp)
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106
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107 ; GP64-NOT-R6: ddiv $zero, $4, $5
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108 ; GP64-NOT-R6: teq $5, $zero, 7
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109 ; GP64-NOT-R6: mfhi $2
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110
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111 ; 64R6: dmod $2, $4, $5
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112 ; 64R6: teq $5, $zero, 7
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113
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114 %r = srem i64 %a, %b
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115 ret i64 %r
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116 }
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117
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118 define signext i128 @srem_i128(i128 signext %a, i128 signext %b) {
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119 entry:
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120 ; ALL-LABEL: srem_i128:
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121
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122 ; GP32: lw $25, %call16(__modti3)($gp)
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123
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124 ; GP64-NOT-R6: ld $25, %call16(__modti3)($gp)
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125 ; 64-R6: ld $25, %call16(__modti3)($gp)
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126
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127 %r = srem i128 %a, %b
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128 ret i128 %r
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129 }
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