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1 //===---------------------------- Context.cpp -------------------*- C++ -*-===//
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2 //
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3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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4 // See https://llvm.org/LICENSE.txt for license information.
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5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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6 //
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7 //===----------------------------------------------------------------------===//
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8 /// \file
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9 ///
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10 /// This file defines a class for holding ownership of various simulated
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11 /// hardware units. A Context also provides a utility routine for constructing
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12 /// a default out-of-order pipeline with fetch, dispatch, execute, and retire
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13 /// stages.
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14 ///
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15 //===----------------------------------------------------------------------===//
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16
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17 #include "llvm/MCA/Context.h"
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18 #include "llvm/MCA/HardwareUnits/RegisterFile.h"
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19 #include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
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20 #include "llvm/MCA/HardwareUnits/Scheduler.h"
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21 #include "llvm/MCA/Stages/DispatchStage.h"
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22 #include "llvm/MCA/Stages/EntryStage.h"
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23 #include "llvm/MCA/Stages/ExecuteStage.h"
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24 #include "llvm/MCA/Stages/MicroOpQueueStage.h"
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25 #include "llvm/MCA/Stages/RetireStage.h"
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26
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27 namespace llvm {
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28 namespace mca {
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29
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30 std::unique_ptr<Pipeline>
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31 Context::createDefaultPipeline(const PipelineOptions &Opts, SourceMgr &SrcMgr) {
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32 const MCSchedModel &SM = STI.getSchedModel();
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33
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34 // Create the hardware units defining the backend.
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35 auto RCU = llvm::make_unique<RetireControlUnit>(SM);
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36 auto PRF = llvm::make_unique<RegisterFile>(SM, MRI, Opts.RegisterFileSize);
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37 auto LSU = llvm::make_unique<LSUnit>(SM, Opts.LoadQueueSize,
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38 Opts.StoreQueueSize, Opts.AssumeNoAlias);
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39 auto HWS = llvm::make_unique<Scheduler>(SM, *LSU);
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40
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41 // Create the pipeline stages.
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42 auto Fetch = llvm::make_unique<EntryStage>(SrcMgr);
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43 auto Dispatch = llvm::make_unique<DispatchStage>(STI, MRI, Opts.DispatchWidth,
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44 *RCU, *PRF);
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45 auto Execute =
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46 llvm::make_unique<ExecuteStage>(*HWS, Opts.EnableBottleneckAnalysis);
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47 auto Retire = llvm::make_unique<RetireStage>(*RCU, *PRF);
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48
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49 // Pass the ownership of all the hardware units to this Context.
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50 addHardwareUnit(std::move(RCU));
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51 addHardwareUnit(std::move(PRF));
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52 addHardwareUnit(std::move(LSU));
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53 addHardwareUnit(std::move(HWS));
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54
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55 // Build the pipeline.
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56 auto StagePipeline = llvm::make_unique<Pipeline>();
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57 StagePipeline->appendStage(std::move(Fetch));
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58 if (Opts.MicroOpQueueSize)
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59 StagePipeline->appendStage(llvm::make_unique<MicroOpQueueStage>(
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60 Opts.MicroOpQueueSize, Opts.DecodersThroughput));
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61 StagePipeline->appendStage(std::move(Dispatch));
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62 StagePipeline->appendStage(std::move(Execute));
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63 StagePipeline->appendStage(std::move(Retire));
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64 return StagePipeline;
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65 }
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66
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67 } // namespace mca
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68 } // namespace llvm
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