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1 //===--------------------- Instruction.cpp ----------------------*- C++ -*-===//
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2 //
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3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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4 // See https://llvm.org/LICENSE.txt for license information.
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5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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6 //
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7 //===----------------------------------------------------------------------===//
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8 //
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9 // This file defines abstractions used by the Pipeline to model register reads,
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10 // register writes and instructions.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #include "llvm/MCA/Instruction.h"
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15 #include "llvm/Support/Debug.h"
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16 #include "llvm/Support/raw_ostream.h"
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17
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18 namespace llvm {
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19 namespace mca {
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20
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21 void WriteState::writeStartEvent(unsigned IID, unsigned RegID,
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22 unsigned Cycles) {
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23 CRD.IID = IID;
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24 CRD.RegID = RegID;
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25 CRD.Cycles = Cycles;
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26 DependentWriteCyclesLeft = Cycles;
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27 DependentWrite = nullptr;
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28 }
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29
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30 void ReadState::writeStartEvent(unsigned IID, unsigned RegID, unsigned Cycles) {
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31 assert(DependentWrites);
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32 assert(CyclesLeft == UNKNOWN_CYCLES);
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33
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34 // This read may be dependent on more than one write. This typically occurs
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35 // when a definition is the result of multiple writes where at least one
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36 // write does a partial register update.
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37 // The HW is forced to do some extra bookkeeping to track of all the
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38 // dependent writes, and implement a merging scheme for the partial writes.
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39 --DependentWrites;
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40 if (TotalCycles < Cycles) {
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41 CRD.IID = IID;
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42 CRD.RegID = RegID;
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43 CRD.Cycles = Cycles;
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44 TotalCycles = Cycles;
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45 }
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46
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47 if (!DependentWrites) {
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48 CyclesLeft = TotalCycles;
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49 IsReady = !CyclesLeft;
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50 }
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51 }
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52
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53 void WriteState::onInstructionIssued(unsigned IID) {
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54 assert(CyclesLeft == UNKNOWN_CYCLES);
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55 // Update the number of cycles left based on the WriteDescriptor info.
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56 CyclesLeft = getLatency();
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57
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58 // Now that the time left before write-back is known, notify
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59 // all the users.
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60 for (const std::pair<ReadState *, int> &User : Users) {
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61 ReadState *RS = User.first;
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62 unsigned ReadCycles = std::max(0, CyclesLeft - User.second);
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63 RS->writeStartEvent(IID, RegisterID, ReadCycles);
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64 }
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65
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66 // Notify any writes that are in a false dependency with this write.
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67 if (PartialWrite)
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68 PartialWrite->writeStartEvent(IID, RegisterID, CyclesLeft);
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69 }
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70
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71 void WriteState::addUser(unsigned IID, ReadState *User, int ReadAdvance) {
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72 // If CyclesLeft is different than -1, then we don't need to
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73 // update the list of users. We can just notify the user with
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74 // the actual number of cycles left (which may be zero).
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75 if (CyclesLeft != UNKNOWN_CYCLES) {
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76 unsigned ReadCycles = std::max(0, CyclesLeft - ReadAdvance);
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77 User->writeStartEvent(IID, RegisterID, ReadCycles);
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78 return;
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79 }
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80
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81 Users.emplace_back(User, ReadAdvance);
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82 }
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83
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84 void WriteState::addUser(unsigned IID, WriteState *User) {
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85 if (CyclesLeft != UNKNOWN_CYCLES) {
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86 User->writeStartEvent(IID, RegisterID, std::max(0, CyclesLeft));
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87 return;
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88 }
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89
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90 assert(!PartialWrite && "PartialWrite already set!");
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91 PartialWrite = User;
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92 User->setDependentWrite(this);
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93 }
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94
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95 void WriteState::cycleEvent() {
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96 // Note: CyclesLeft can be a negative number. It is an error to
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97 // make it an unsigned quantity because users of this write may
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98 // specify a negative ReadAdvance.
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99 if (CyclesLeft != UNKNOWN_CYCLES)
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100 CyclesLeft--;
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101
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102 if (DependentWriteCyclesLeft)
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103 DependentWriteCyclesLeft--;
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104 }
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105
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106 void ReadState::cycleEvent() {
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107 // Update the total number of cycles.
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108 if (DependentWrites && TotalCycles) {
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109 --TotalCycles;
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110 return;
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111 }
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112
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113 // Bail out immediately if we don't know how many cycles are left.
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114 if (CyclesLeft == UNKNOWN_CYCLES)
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115 return;
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116
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117 if (CyclesLeft) {
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118 --CyclesLeft;
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119 IsReady = !CyclesLeft;
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120 }
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121 }
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122
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123 #ifndef NDEBUG
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124 void WriteState::dump() const {
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125 dbgs() << "{ OpIdx=" << WD->OpIndex << ", Lat=" << getLatency() << ", RegID "
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126 << getRegisterID() << ", Cycles Left=" << getCyclesLeft() << " }";
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127 }
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128
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129 void WriteRef::dump() const {
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130 dbgs() << "IID=" << getSourceIndex() << ' ';
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131 if (isValid())
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132 getWriteState()->dump();
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133 else
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134 dbgs() << "(null)";
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135 }
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136 #endif
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137
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138 const CriticalDependency &Instruction::computeCriticalRegDep() {
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139 if (CriticalRegDep.Cycles)
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140 return CriticalRegDep;
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141
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142 unsigned MaxLatency = 0;
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143 for (const WriteState &WS : getDefs()) {
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144 const CriticalDependency &WriteCRD = WS.getCriticalRegDep();
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145 if (WriteCRD.Cycles > MaxLatency)
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146 CriticalRegDep = WriteCRD;
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147 }
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148
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149 for (const ReadState &RS : getUses()) {
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150 const CriticalDependency &ReadCRD = RS.getCriticalRegDep();
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151 if (ReadCRD.Cycles > MaxLatency)
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152 CriticalRegDep = ReadCRD;
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153 }
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154
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155 return CriticalRegDep;
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156 }
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157
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158 void Instruction::dispatch(unsigned RCUToken) {
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159 assert(Stage == IS_INVALID);
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160 Stage = IS_DISPATCHED;
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161 RCUTokenID = RCUToken;
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162
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163 // Check if input operands are already available.
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164 if (updateDispatched())
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165 updatePending();
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166 }
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167
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168 void Instruction::execute(unsigned IID) {
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169 assert(Stage == IS_READY);
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170 Stage = IS_EXECUTING;
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171
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172 // Set the cycles left before the write-back stage.
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173 CyclesLeft = getLatency();
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174
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175 for (WriteState &WS : getDefs())
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176 WS.onInstructionIssued(IID);
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177
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178 // Transition to the "executed" stage if this is a zero-latency instruction.
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179 if (!CyclesLeft)
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180 Stage = IS_EXECUTED;
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181 }
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182
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183 void Instruction::forceExecuted() {
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184 assert(Stage == IS_READY && "Invalid internal state!");
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185 CyclesLeft = 0;
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186 Stage = IS_EXECUTED;
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187 }
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188
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189 bool Instruction::updatePending() {
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190 assert(isPending() && "Unexpected instruction stage found!");
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191
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192 if (!all_of(getUses(), [](const ReadState &Use) { return Use.isReady(); }))
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193 return false;
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194
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195 // A partial register write cannot complete before a dependent write.
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196 if (!all_of(getDefs(), [](const WriteState &Def) { return Def.isReady(); }))
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197 return false;
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198
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199 Stage = IS_READY;
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200 return true;
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201 }
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202
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203 bool Instruction::updateDispatched() {
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204 assert(isDispatched() && "Unexpected instruction stage found!");
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205
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206 if (!all_of(getUses(), [](const ReadState &Use) {
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207 return Use.isPending() || Use.isReady();
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208 }))
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209 return false;
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210
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211 // A partial register write cannot complete before a dependent write.
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212 if (!all_of(getDefs(),
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213 [](const WriteState &Def) { return !Def.getDependentWrite(); }))
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214 return false;
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215
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216 Stage = IS_PENDING;
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217 return true;
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218 }
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219
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220 void Instruction::update() {
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221 if (isDispatched())
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222 updateDispatched();
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223 if (isPending())
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224 updatePending();
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225 }
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226
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227 void Instruction::cycleEvent() {
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228 if (isReady())
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229 return;
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230
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231 if (isDispatched() || isPending()) {
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232 for (ReadState &Use : getUses())
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233 Use.cycleEvent();
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234
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235 for (WriteState &Def : getDefs())
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236 Def.cycleEvent();
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237
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238 update();
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239 return;
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240 }
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241
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242 assert(isExecuting() && "Instruction not in-flight?");
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243 assert(CyclesLeft && "Instruction already executed?");
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244 for (WriteState &Def : getDefs())
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245 Def.cycleEvent();
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246 CyclesLeft--;
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247 if (!CyclesLeft)
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248 Stage = IS_EXECUTED;
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249 }
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250
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251 const unsigned WriteRef::INVALID_IID = std::numeric_limits<unsigned>::max();
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252
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253 } // namespace mca
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254 } // namespace llvm
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