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annotate lib/Target/ARM/ARMFeatures.h @ 148:63bd29f05246

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merged
author Shinji KONO <kono@ie.u-ryukyu.ac.jp>
date Wed, 14 Aug 2019 19:46:37 +0900
parents c2174574ed3a
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 //===-- ARMFeatures.h - Checks for ARM instruction features -----*- C++ -*-===//
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2 //
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3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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4 // See https://llvm.org/LICENSE.txt for license information.
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5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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6 //
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7 //===----------------------------------------------------------------------===//
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8 //
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9 // This file contains the code shared between ARM CodeGen and ARM MC
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10 //
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11 //===----------------------------------------------------------------------===//
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12
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13 #ifndef LLVM_LIB_TARGET_ARM_ARMFEATURES_H
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14 #define LLVM_LIB_TARGET_ARM_ARMFEATURES_H
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15
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16 #include "MCTargetDesc/ARMMCTargetDesc.h"
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17
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18 namespace llvm {
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19
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20 template<typename InstrType> // could be MachineInstr or MCInst
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21 bool IsCPSRDead(const InstrType *Instr);
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22
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23 template<typename InstrType> // could be MachineInstr or MCInst
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24 inline bool isV8EligibleForIT(const InstrType *Instr) {
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25 switch (Instr->getOpcode()) {
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26 default:
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27 return false;
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28 case ARM::tADC:
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29 case ARM::tADDi3:
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30 case ARM::tADDi8:
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31 case ARM::tADDrr:
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32 case ARM::tAND:
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33 case ARM::tASRri:
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34 case ARM::tASRrr:
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35 case ARM::tBIC:
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36 case ARM::tEOR:
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37 case ARM::tLSLri:
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38 case ARM::tLSLrr:
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39 case ARM::tLSRri:
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40 case ARM::tLSRrr:
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41 case ARM::tMOVi8:
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42 case ARM::tMUL:
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43 case ARM::tMVN:
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44 case ARM::tORR:
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45 case ARM::tROR:
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46 case ARM::tRSB:
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47 case ARM::tSBC:
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48 case ARM::tSUBi3:
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49 case ARM::tSUBi8:
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50 case ARM::tSUBrr:
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51 // Outside of an IT block, these set CPSR.
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52 return IsCPSRDead(Instr);
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53 case ARM::tADDrSPi:
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54 case ARM::tCMNz:
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55 case ARM::tCMPi8:
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56 case ARM::tCMPr:
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57 case ARM::tLDRBi:
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58 case ARM::tLDRBr:
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59 case ARM::tLDRHi:
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60 case ARM::tLDRHr:
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61 case ARM::tLDRSB:
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62 case ARM::tLDRSH:
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63 case ARM::tLDRi:
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64 case ARM::tLDRr:
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65 case ARM::tLDRspi:
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66 case ARM::tSTRBi:
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67 case ARM::tSTRBr:
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68 case ARM::tSTRHi:
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69 case ARM::tSTRHr:
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70 case ARM::tSTRi:
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71 case ARM::tSTRr:
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72 case ARM::tSTRspi:
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73 case ARM::tTST:
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74 return true;
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75 // there are some "conditionally deprecated" opcodes
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76 case ARM::tADDspr:
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77 case ARM::tBLXr:
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78 return Instr->getOperand(2).getReg() != ARM::PC;
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79 // ADD PC, SP and BLX PC were always unpredictable,
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80 // now on top of it they're deprecated
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81 case ARM::tADDrSP:
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82 case ARM::tBX:
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83 return Instr->getOperand(0).getReg() != ARM::PC;
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84 case ARM::tADDhirr:
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85 return Instr->getOperand(0).getReg() != ARM::PC &&
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86 Instr->getOperand(2).getReg() != ARM::PC;
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87 case ARM::tCMPhir:
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88 case ARM::tMOVr:
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89 return Instr->getOperand(0).getReg() != ARM::PC &&
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90 Instr->getOperand(1).getReg() != ARM::PC;
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91 }
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92 }
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93
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94 }
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95
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96 #endif