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1 //===- ARMTargetTransformInfo.h - ARM specific TTI --------------*- C++ -*-===//
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2 //
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3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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4 // See https://llvm.org/LICENSE.txt for license information.
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5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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6 //
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7 //===----------------------------------------------------------------------===//
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8 //
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9 /// \file
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10 /// This file a TargetTransformInfo::Concept conforming object specific to the
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11 /// ARM target machine. It uses the target's detailed information to
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12 /// provide more precise answers to certain TTI queries, while letting the
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13 /// target independent and default TTI implementations handle the rest.
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14 //
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15 //===----------------------------------------------------------------------===//
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16
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17 #ifndef LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
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18 #define LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
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19
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20 #include "ARM.h"
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21 #include "ARMSubtarget.h"
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22 #include "ARMTargetMachine.h"
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23 #include "llvm/ADT/ArrayRef.h"
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24 #include "llvm/Analysis/TargetTransformInfo.h"
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25 #include "llvm/CodeGen/BasicTTIImpl.h"
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26 #include "llvm/IR/Constant.h"
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27 #include "llvm/IR/Function.h"
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28 #include "llvm/MC/SubtargetFeature.h"
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29
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30 namespace llvm {
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31
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32 class APInt;
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33 class ARMTargetLowering;
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34 class Instruction;
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35 class Loop;
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36 class SCEV;
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37 class ScalarEvolution;
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38 class Type;
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39 class Value;
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40
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41 class ARMTTIImpl : public BasicTTIImplBase<ARMTTIImpl> {
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42 using BaseT = BasicTTIImplBase<ARMTTIImpl>;
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43 using TTI = TargetTransformInfo;
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44
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45 friend BaseT;
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46
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47 const ARMSubtarget *ST;
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48 const ARMTargetLowering *TLI;
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49
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50 // Currently the following features are excluded from InlineFeatureWhitelist.
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51 // ModeThumb, FeatureNoARM, ModeSoftFloat, FeatureFP64, FeatureD32
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52 // Depending on whether they are set or unset, different
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53 // instructions/registers are available. For example, inlining a callee with
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54 // -thumb-mode in a caller with +thumb-mode, may cause the assembler to
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55 // fail if the callee uses ARM only instructions, e.g. in inline asm.
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56 const FeatureBitset InlineFeatureWhitelist = {
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57 ARM::FeatureVFP2, ARM::FeatureVFP3, ARM::FeatureNEON, ARM::FeatureThumb2,
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58 ARM::FeatureFP16, ARM::FeatureVFP4, ARM::FeatureFPARMv8,
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59 ARM::FeatureFullFP16, ARM::FeatureFP16FML, ARM::FeatureHWDivThumb,
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60 ARM::FeatureHWDivARM, ARM::FeatureDB, ARM::FeatureV7Clrex,
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61 ARM::FeatureAcquireRelease, ARM::FeatureSlowFPBrcc,
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62 ARM::FeaturePerfMon, ARM::FeatureTrustZone, ARM::Feature8MSecExt,
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63 ARM::FeatureCrypto, ARM::FeatureCRC, ARM::FeatureRAS,
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64 ARM::FeatureFPAO, ARM::FeatureFuseAES, ARM::FeatureZCZeroing,
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65 ARM::FeatureProfUnpredicate, ARM::FeatureSlowVGETLNi32,
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66 ARM::FeatureSlowVDUP32, ARM::FeaturePreferVMOVSR,
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67 ARM::FeaturePrefISHSTBarrier, ARM::FeatureMuxedUnits,
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68 ARM::FeatureSlowOddRegister, ARM::FeatureSlowLoadDSubreg,
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69 ARM::FeatureDontWidenVMOVS, ARM::FeatureExpandMLx,
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70 ARM::FeatureHasVMLxHazards, ARM::FeatureNEONForFPMovs,
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71 ARM::FeatureNEONForFP, ARM::FeatureCheckVLDnAlign,
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72 ARM::FeatureHasSlowFPVMLx, ARM::FeatureVMLxForwarding,
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73 ARM::FeaturePref32BitThumb, ARM::FeatureAvoidPartialCPSR,
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74 ARM::FeatureCheapPredicableCPSR, ARM::FeatureAvoidMOVsShOp,
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75 ARM::FeatureHasRetAddrStack, ARM::FeatureHasNoBranchPredictor,
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76 ARM::FeatureDSP, ARM::FeatureMP, ARM::FeatureVirtualization,
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77 ARM::FeatureMClass, ARM::FeatureRClass, ARM::FeatureAClass,
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78 ARM::FeatureNaClTrap, ARM::FeatureStrictAlign, ARM::FeatureLongCalls,
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79 ARM::FeatureExecuteOnly, ARM::FeatureReserveR9, ARM::FeatureNoMovt,
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80 ARM::FeatureNoNegativeImmediates
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81 };
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82
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83 const ARMSubtarget *getST() const { return ST; }
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84 const ARMTargetLowering *getTLI() const { return TLI; }
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85
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86 public:
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87 explicit ARMTTIImpl(const ARMBaseTargetMachine *TM, const Function &F)
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88 : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
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89 TLI(ST->getTargetLowering()) {}
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90
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91 bool areInlineCompatible(const Function *Caller,
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92 const Function *Callee) const;
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93
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94 bool enableInterleavedAccessVectorization() { return true; }
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95
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96 bool shouldFavorBackedgeIndex(const Loop *L) const {
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97 if (L->getHeader()->getParent()->hasOptSize())
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98 return false;
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99 return ST->isMClass() && ST->isThumb2() && L->getNumBlocks() == 1;
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100 }
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101
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102 /// Floating-point computation using ARMv8 AArch32 Advanced
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103 /// SIMD instructions remains unchanged from ARMv7. Only AArch64 SIMD
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104 /// and Arm MVE are IEEE-754 compliant.
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105 bool isFPVectorizationPotentiallyUnsafe() {
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106 return !ST->isTargetDarwin() && !ST->hasMVEFloatOps();
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107 }
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108
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109 /// \name Scalar TTI Implementations
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110 /// @{
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111
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112 int getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
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113 Type *Ty);
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114
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115 using BaseT::getIntImmCost;
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116 int getIntImmCost(const APInt &Imm, Type *Ty);
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117
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118 int getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty);
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119
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120 /// @}
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122 /// \name Vector TTI Implementations
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123 /// @{
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124
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125 unsigned getNumberOfRegisters(bool Vector) {
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126 if (Vector) {
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127 if (ST->hasNEON())
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128 return 16;
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129 if (ST->hasMVEIntegerOps())
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130 return 8;
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131 return 0;
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132 }
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133
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134 if (ST->isThumb1Only())
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135 return 8;
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136 return 13;
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137 }
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138
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139 unsigned getRegisterBitWidth(bool Vector) const {
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140 if (Vector) {
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141 if (ST->hasNEON())
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142 return 128;
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143 if (ST->hasMVEIntegerOps())
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144 return 128;
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145 return 0;
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146 }
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147
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148 return 32;
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149 }
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150
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151 unsigned getMaxInterleaveFactor(unsigned VF) {
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152 return ST->getMaxInterleaveFactor();
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153 }
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154
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155 int getMemcpyCost(const Instruction *I);
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156
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157 int getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, int Index, Type *SubTp);
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158
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159 int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
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160 const Instruction *I = nullptr);
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161
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162 int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
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163 const Instruction *I = nullptr);
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164
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165 int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
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166
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167 int getAddressComputationCost(Type *Val, ScalarEvolution *SE,
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168 const SCEV *Ptr);
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169
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170 int getArithmeticInstrCost(
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171 unsigned Opcode, Type *Ty,
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172 TTI::OperandValueKind Op1Info = TTI::OK_AnyValue,
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173 TTI::OperandValueKind Op2Info = TTI::OK_AnyValue,
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174 TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
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175 TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None,
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176 ArrayRef<const Value *> Args = ArrayRef<const Value *>());
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177
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178 int getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
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179 unsigned AddressSpace, const Instruction *I = nullptr);
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180
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181 int getInterleavedMemoryOpCost(unsigned Opcode, Type *VecTy, unsigned Factor,
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182 ArrayRef<unsigned> Indices, unsigned Alignment,
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183 unsigned AddressSpace,
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184 bool UseMaskForCond = false,
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185 bool UseMaskForGaps = false);
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186
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187 bool isLoweredToCall(const Function *F);
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188 bool isHardwareLoopProfitable(Loop *L, ScalarEvolution &SE,
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189 AssumptionCache &AC,
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190 TargetLibraryInfo *LibInfo,
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191 HardwareLoopInfo &HWLoopInfo);
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192
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193 void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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194 TTI::UnrollingPreferences &UP);
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195
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196 bool shouldBuildLookupTablesForConstant(Constant *C) const {
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197 // In the ROPI and RWPI relocation models we can't have pointers to global
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198 // variables or functions in constant data, so don't convert switches to
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199 // lookup tables if any of the values would need relocation.
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200 if (ST->isROPI() || ST->isRWPI())
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201 return !C->needsRelocation();
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202
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203 return true;
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204 }
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205 /// @}
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206 };
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207
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208 } // end namespace llvm
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209
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210 #endif // LLVM_LIB_TARGET_ARM_ARMTARGETTRANSFORMINFO_H
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