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1 //===-- AVRInstrInfo.cpp - AVR Instruction Information --------------------===//
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2 //
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147
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3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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4 // See https://llvm.org/LICENSE.txt for license information.
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5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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120
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6 //
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7 //===----------------------------------------------------------------------===//
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8 //
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9 // This file contains the AVR implementation of the TargetInstrInfo class.
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10 //
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11 //===----------------------------------------------------------------------===//
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12
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13 #include "AVRInstrInfo.h"
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14
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15 #include "llvm/ADT/STLExtras.h"
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16 #include "llvm/CodeGen/MachineConstantPool.h"
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17 #include "llvm/CodeGen/MachineFrameInfo.h"
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18 #include "llvm/CodeGen/MachineInstrBuilder.h"
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19 #include "llvm/CodeGen/MachineMemOperand.h"
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20 #include "llvm/IR/Constants.h"
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21 #include "llvm/IR/Function.h"
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22 #include "llvm/MC/MCContext.h"
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23 #include "llvm/Support/Debug.h"
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24 #include "llvm/Support/ErrorHandling.h"
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25 #include "llvm/Support/TargetRegistry.h"
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26
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27 #include "AVR.h"
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28 #include "AVRMachineFunctionInfo.h"
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29 #include "AVRRegisterInfo.h"
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30 #include "AVRTargetMachine.h"
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31 #include "MCTargetDesc/AVRMCTargetDesc.h"
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32
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33 #define GET_INSTRINFO_CTOR_DTOR
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34 #include "AVRGenInstrInfo.inc"
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35
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36 namespace llvm {
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37
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38 AVRInstrInfo::AVRInstrInfo()
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39 : AVRGenInstrInfo(AVR::ADJCALLSTACKDOWN, AVR::ADJCALLSTACKUP), RI() {}
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40
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41 void AVRInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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42 MachineBasicBlock::iterator MI,
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43 const DebugLoc &DL, unsigned DestReg,
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44 unsigned SrcReg, bool KillSrc) const {
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45 const AVRSubtarget &STI = MBB.getParent()->getSubtarget<AVRSubtarget>();
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46 const AVRRegisterInfo &TRI = *STI.getRegisterInfo();
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47 unsigned Opc;
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48
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49 // Not all AVR devices support the 16-bit `MOVW` instruction.
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50 if (AVR::DREGSRegClass.contains(DestReg, SrcReg)) {
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51 if (STI.hasMOVW()) {
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52 BuildMI(MBB, MI, DL, get(AVR::MOVWRdRr), DestReg)
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53 .addReg(SrcReg, getKillRegState(KillSrc));
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54 } else {
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55 unsigned DestLo, DestHi, SrcLo, SrcHi;
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56
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57 TRI.splitReg(DestReg, DestLo, DestHi);
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58 TRI.splitReg(SrcReg, SrcLo, SrcHi);
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59
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60 // Copy each individual register with the `MOV` instruction.
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61 BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestLo)
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62 .addReg(SrcLo, getKillRegState(KillSrc));
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63 BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestHi)
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64 .addReg(SrcHi, getKillRegState(KillSrc));
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65 }
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66 } else {
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67 if (AVR::GPR8RegClass.contains(DestReg, SrcReg)) {
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68 Opc = AVR::MOVRdRr;
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69 } else if (SrcReg == AVR::SP && AVR::DREGSRegClass.contains(DestReg)) {
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70 Opc = AVR::SPREAD;
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71 } else if (DestReg == AVR::SP && AVR::DREGSRegClass.contains(SrcReg)) {
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72 Opc = AVR::SPWRITE;
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73 } else {
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74 llvm_unreachable("Impossible reg-to-reg copy");
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75 }
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76
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77 BuildMI(MBB, MI, DL, get(Opc), DestReg)
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78 .addReg(SrcReg, getKillRegState(KillSrc));
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79 }
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80 }
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81
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82 unsigned AVRInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
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83 int &FrameIndex) const {
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84 switch (MI.getOpcode()) {
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85 case AVR::LDDRdPtrQ:
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86 case AVR::LDDWRdYQ: { //:FIXME: remove this once PR13375 gets fixed
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87 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
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88 MI.getOperand(2).getImm() == 0) {
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89 FrameIndex = MI.getOperand(1).getIndex();
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90 return MI.getOperand(0).getReg();
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91 }
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92 break;
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93 }
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94 default:
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95 break;
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96 }
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97
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98 return 0;
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99 }
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100
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101 unsigned AVRInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
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102 int &FrameIndex) const {
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103 switch (MI.getOpcode()) {
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104 case AVR::STDPtrQRr:
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105 case AVR::STDWPtrQRr: {
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106 if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
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107 MI.getOperand(1).getImm() == 0) {
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108 FrameIndex = MI.getOperand(0).getIndex();
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109 return MI.getOperand(2).getReg();
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110 }
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111 break;
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112 }
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113 default:
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114 break;
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115 }
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116
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117 return 0;
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118 }
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119
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120 void AVRInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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121 MachineBasicBlock::iterator MI,
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122 unsigned SrcReg, bool isKill,
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123 int FrameIndex,
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124 const TargetRegisterClass *RC,
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125 const TargetRegisterInfo *TRI) const {
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126 MachineFunction &MF = *MBB.getParent();
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127 AVRMachineFunctionInfo *AFI = MF.getInfo<AVRMachineFunctionInfo>();
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128
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129 AFI->setHasSpills(true);
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130
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131 DebugLoc DL;
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132 if (MI != MBB.end()) {
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133 DL = MI->getDebugLoc();
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134 }
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135
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136 const MachineFrameInfo &MFI = MF.getFrameInfo();
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137
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138 MachineMemOperand *MMO = MF.getMachineMemOperand(
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139 MachinePointerInfo::getFixedStack(MF, FrameIndex),
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140 MachineMemOperand::MOStore, MFI.getObjectSize(FrameIndex),
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141 MFI.getObjectAlignment(FrameIndex));
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142
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143 unsigned Opcode = 0;
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121
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144 if (TRI->isTypeLegalForClass(*RC, MVT::i8)) {
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120
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145 Opcode = AVR::STDPtrQRr;
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121
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146 } else if (TRI->isTypeLegalForClass(*RC, MVT::i16)) {
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120
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147 Opcode = AVR::STDWPtrQRr;
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148 } else {
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149 llvm_unreachable("Cannot store this register into a stack slot!");
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150 }
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151
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152 BuildMI(MBB, MI, DL, get(Opcode))
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153 .addFrameIndex(FrameIndex)
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154 .addImm(0)
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155 .addReg(SrcReg, getKillRegState(isKill))
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156 .addMemOperand(MMO);
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157 }
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158
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159 void AVRInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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160 MachineBasicBlock::iterator MI,
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161 unsigned DestReg, int FrameIndex,
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162 const TargetRegisterClass *RC,
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163 const TargetRegisterInfo *TRI) const {
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164 DebugLoc DL;
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165 if (MI != MBB.end()) {
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166 DL = MI->getDebugLoc();
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167 }
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168
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169 MachineFunction &MF = *MBB.getParent();
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170 const MachineFrameInfo &MFI = MF.getFrameInfo();
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171
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172 MachineMemOperand *MMO = MF.getMachineMemOperand(
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173 MachinePointerInfo::getFixedStack(MF, FrameIndex),
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174 MachineMemOperand::MOLoad, MFI.getObjectSize(FrameIndex),
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175 MFI.getObjectAlignment(FrameIndex));
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176
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177 unsigned Opcode = 0;
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121
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178 if (TRI->isTypeLegalForClass(*RC, MVT::i8)) {
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120
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179 Opcode = AVR::LDDRdPtrQ;
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121
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180 } else if (TRI->isTypeLegalForClass(*RC, MVT::i16)) {
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120
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181 // Opcode = AVR::LDDWRdPtrQ;
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182 //:FIXME: remove this once PR13375 gets fixed
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183 Opcode = AVR::LDDWRdYQ;
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184 } else {
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185 llvm_unreachable("Cannot load this register from a stack slot!");
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186 }
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187
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188 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
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189 .addFrameIndex(FrameIndex)
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190 .addImm(0)
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191 .addMemOperand(MMO);
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192 }
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193
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194 const MCInstrDesc &AVRInstrInfo::getBrCond(AVRCC::CondCodes CC) const {
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195 switch (CC) {
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196 default:
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197 llvm_unreachable("Unknown condition code!");
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198 case AVRCC::COND_EQ:
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199 return get(AVR::BREQk);
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200 case AVRCC::COND_NE:
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201 return get(AVR::BRNEk);
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202 case AVRCC::COND_GE:
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203 return get(AVR::BRGEk);
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204 case AVRCC::COND_LT:
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205 return get(AVR::BRLTk);
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206 case AVRCC::COND_SH:
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207 return get(AVR::BRSHk);
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208 case AVRCC::COND_LO:
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209 return get(AVR::BRLOk);
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210 case AVRCC::COND_MI:
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211 return get(AVR::BRMIk);
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212 case AVRCC::COND_PL:
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213 return get(AVR::BRPLk);
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214 }
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215 }
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216
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217 AVRCC::CondCodes AVRInstrInfo::getCondFromBranchOpc(unsigned Opc) const {
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218 switch (Opc) {
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219 default:
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220 return AVRCC::COND_INVALID;
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221 case AVR::BREQk:
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222 return AVRCC::COND_EQ;
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223 case AVR::BRNEk:
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224 return AVRCC::COND_NE;
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225 case AVR::BRSHk:
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226 return AVRCC::COND_SH;
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227 case AVR::BRLOk:
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228 return AVRCC::COND_LO;
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229 case AVR::BRMIk:
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230 return AVRCC::COND_MI;
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231 case AVR::BRPLk:
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232 return AVRCC::COND_PL;
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233 case AVR::BRGEk:
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234 return AVRCC::COND_GE;
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235 case AVR::BRLTk:
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236 return AVRCC::COND_LT;
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237 }
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238 }
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239
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240 AVRCC::CondCodes AVRInstrInfo::getOppositeCondition(AVRCC::CondCodes CC) const {
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241 switch (CC) {
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242 default:
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243 llvm_unreachable("Invalid condition!");
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244 case AVRCC::COND_EQ:
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245 return AVRCC::COND_NE;
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246 case AVRCC::COND_NE:
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247 return AVRCC::COND_EQ;
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248 case AVRCC::COND_SH:
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249 return AVRCC::COND_LO;
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250 case AVRCC::COND_LO:
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251 return AVRCC::COND_SH;
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252 case AVRCC::COND_GE:
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253 return AVRCC::COND_LT;
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254 case AVRCC::COND_LT:
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255 return AVRCC::COND_GE;
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256 case AVRCC::COND_MI:
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257 return AVRCC::COND_PL;
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258 case AVRCC::COND_PL:
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259 return AVRCC::COND_MI;
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260 }
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261 }
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262
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263 bool AVRInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
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264 MachineBasicBlock *&TBB,
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265 MachineBasicBlock *&FBB,
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266 SmallVectorImpl<MachineOperand> &Cond,
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267 bool AllowModify) const {
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268 // Start from the bottom of the block and work up, examining the
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269 // terminator instructions.
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270 MachineBasicBlock::iterator I = MBB.end();
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271 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
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272
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273 while (I != MBB.begin()) {
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274 --I;
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147
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275 if (I->isDebugInstr()) {
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120
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276 continue;
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277 }
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278
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279 // Working from the bottom, when we see a non-terminator
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280 // instruction, we're done.
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281 if (!isUnpredicatedTerminator(*I)) {
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282 break;
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283 }
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284
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285 // A terminator that isn't a branch can't easily be handled
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286 // by this analysis.
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287 if (!I->getDesc().isBranch()) {
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288 return true;
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289 }
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290
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291 // Handle unconditional branches.
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292 //:TODO: add here jmp
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293 if (I->getOpcode() == AVR::RJMPk) {
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294 UnCondBrIter = I;
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295
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296 if (!AllowModify) {
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297 TBB = I->getOperand(0).getMBB();
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298 continue;
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299 }
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300
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301 // If the block has any instructions after a JMP, delete them.
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302 while (std::next(I) != MBB.end()) {
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303 std::next(I)->eraseFromParent();
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304 }
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305
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306 Cond.clear();
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307 FBB = 0;
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308
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309 // Delete the JMP if it's equivalent to a fall-through.
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310 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
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311 TBB = 0;
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312 I->eraseFromParent();
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313 I = MBB.end();
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314 UnCondBrIter = MBB.end();
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315 continue;
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316 }
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317
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318 // TBB is used to indicate the unconditinal destination.
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319 TBB = I->getOperand(0).getMBB();
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320 continue;
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321 }
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322
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323 // Handle conditional branches.
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324 AVRCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode());
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325 if (BranchCode == AVRCC::COND_INVALID) {
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326 return true; // Can't handle indirect branch.
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327 }
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328
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329 // Working from the bottom, handle the first conditional branch.
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330 if (Cond.empty()) {
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331 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
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332 if (AllowModify && UnCondBrIter != MBB.end() &&
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333 MBB.isLayoutSuccessor(TargetBB)) {
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334 // If we can modify the code and it ends in something like:
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335 //
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336 // jCC L1
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337 // jmp L2
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338 // L1:
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339 // ...
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340 // L2:
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341 //
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342 // Then we can change this to:
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343 //
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344 // jnCC L2
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345 // L1:
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346 // ...
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347 // L2:
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348 //
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349 // Which is a bit more efficient.
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350 // We conditionally jump to the fall-through block.
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351 BranchCode = getOppositeCondition(BranchCode);
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352 unsigned JNCC = getBrCond(BranchCode).getOpcode();
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353 MachineBasicBlock::iterator OldInst = I;
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354
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355 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
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356 .addMBB(UnCondBrIter->getOperand(0).getMBB());
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357 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(AVR::RJMPk))
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358 .addMBB(TargetBB);
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359
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360 OldInst->eraseFromParent();
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361 UnCondBrIter->eraseFromParent();
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362
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363 // Restart the analysis.
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364 UnCondBrIter = MBB.end();
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365 I = MBB.end();
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366 continue;
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367 }
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368
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369 FBB = TBB;
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370 TBB = I->getOperand(0).getMBB();
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371 Cond.push_back(MachineOperand::CreateImm(BranchCode));
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372 continue;
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373 }
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374
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375 // Handle subsequent conditional branches. Only handle the case where all
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376 // conditional branches branch to the same destination.
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377 assert(Cond.size() == 1);
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378 assert(TBB);
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379
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380 // Only handle the case where all conditional branches branch to
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381 // the same destination.
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382 if (TBB != I->getOperand(0).getMBB()) {
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383 return true;
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384 }
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385
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386 AVRCC::CondCodes OldBranchCode = (AVRCC::CondCodes)Cond[0].getImm();
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387 // If the conditions are the same, we can leave them alone.
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388 if (OldBranchCode == BranchCode) {
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389 continue;
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390 }
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391
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392 return true;
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393 }
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394
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395 return false;
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396 }
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397
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398 unsigned AVRInstrInfo::insertBranch(MachineBasicBlock &MBB,
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399 MachineBasicBlock *TBB,
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400 MachineBasicBlock *FBB,
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401 ArrayRef<MachineOperand> Cond,
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402 const DebugLoc &DL,
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403 int *BytesAdded) const {
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121
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404 if (BytesAdded) *BytesAdded = 0;
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120
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405
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406 // Shouldn't be a fall through.
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407 assert(TBB && "insertBranch must not be told to insert a fallthrough");
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408 assert((Cond.size() == 1 || Cond.size() == 0) &&
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409 "AVR branch conditions have one component!");
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410
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411 if (Cond.empty()) {
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412 assert(!FBB && "Unconditional branch with multiple successors!");
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121
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413 auto &MI = *BuildMI(&MBB, DL, get(AVR::RJMPk)).addMBB(TBB);
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414 if (BytesAdded)
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415 *BytesAdded += getInstSizeInBytes(MI);
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120
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416 return 1;
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417 }
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418
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419 // Conditional branch.
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420 unsigned Count = 0;
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421 AVRCC::CondCodes CC = (AVRCC::CondCodes)Cond[0].getImm();
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121
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422 auto &CondMI = *BuildMI(&MBB, DL, getBrCond(CC)).addMBB(TBB);
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423
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424 if (BytesAdded) *BytesAdded += getInstSizeInBytes(CondMI);
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120
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425 ++Count;
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426
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427 if (FBB) {
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428 // Two-way Conditional branch. Insert the second branch.
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121
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429 auto &MI = *BuildMI(&MBB, DL, get(AVR::RJMPk)).addMBB(FBB);
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430 if (BytesAdded) *BytesAdded += getInstSizeInBytes(MI);
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120
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431 ++Count;
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432 }
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433
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434 return Count;
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435 }
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436
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437 unsigned AVRInstrInfo::removeBranch(MachineBasicBlock &MBB,
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438 int *BytesRemoved) const {
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121
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439 if (BytesRemoved) *BytesRemoved = 0;
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120
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440
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441 MachineBasicBlock::iterator I = MBB.end();
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442 unsigned Count = 0;
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443
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444 while (I != MBB.begin()) {
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445 --I;
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147
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446 if (I->isDebugInstr()) {
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120
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447 continue;
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448 }
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449 //:TODO: add here the missing jmp instructions once they are implemented
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450 // like jmp, {e}ijmp, and other cond branches, ...
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451 if (I->getOpcode() != AVR::RJMPk &&
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452 getCondFromBranchOpc(I->getOpcode()) == AVRCC::COND_INVALID) {
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453 break;
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454 }
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455
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456 // Remove the branch.
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121
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457 if (BytesRemoved) *BytesRemoved += getInstSizeInBytes(*I);
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120
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458 I->eraseFromParent();
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459 I = MBB.end();
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460 ++Count;
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461 }
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462
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463 return Count;
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464 }
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465
|
|
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466 bool AVRInstrInfo::reverseBranchCondition(
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467 SmallVectorImpl<MachineOperand> &Cond) const {
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|
|
468 assert(Cond.size() == 1 && "Invalid AVR branch condition!");
|
|
|
469
|
|
|
470 AVRCC::CondCodes CC = static_cast<AVRCC::CondCodes>(Cond[0].getImm());
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|
|
471 Cond[0].setImm(getOppositeCondition(CC));
|
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472
|
|
|
473 return false;
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|
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474 }
|
|
|
475
|
|
|
476 unsigned AVRInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
|
|
|
477 unsigned Opcode = MI.getOpcode();
|
|
|
478
|
|
|
479 switch (Opcode) {
|
|
|
480 // A regular instruction
|
|
|
481 default: {
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|
|
482 const MCInstrDesc &Desc = get(Opcode);
|
|
|
483 return Desc.getSize();
|
|
|
484 }
|
|
|
485 case TargetOpcode::EH_LABEL:
|
|
|
486 case TargetOpcode::IMPLICIT_DEF:
|
|
|
487 case TargetOpcode::KILL:
|
|
|
488 case TargetOpcode::DBG_VALUE:
|
|
|
489 return 0;
|
|
147
|
490 case TargetOpcode::INLINEASM:
|
|
|
491 case TargetOpcode::INLINEASM_BR: {
|
|
120
|
492 const MachineFunction &MF = *MI.getParent()->getParent();
|
|
|
493 const AVRTargetMachine &TM = static_cast<const AVRTargetMachine&>(MF.getTarget());
|
|
|
494 const AVRSubtarget &STI = MF.getSubtarget<AVRSubtarget>();
|
|
|
495 const TargetInstrInfo &TII = *STI.getInstrInfo();
|
|
|
496
|
|
|
497 return TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
|
|
|
498 *TM.getMCAsmInfo());
|
|
|
499 }
|
|
|
500 }
|
|
|
501 }
|
|
|
502
|
|
121
|
503 MachineBasicBlock *
|
|
|
504 AVRInstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
|
|
|
505 switch (MI.getOpcode()) {
|
|
|
506 default:
|
|
|
507 llvm_unreachable("unexpected opcode!");
|
|
|
508 case AVR::JMPk:
|
|
|
509 case AVR::CALLk:
|
|
|
510 case AVR::RCALLk:
|
|
|
511 case AVR::RJMPk:
|
|
|
512 case AVR::BREQk:
|
|
|
513 case AVR::BRNEk:
|
|
|
514 case AVR::BRSHk:
|
|
|
515 case AVR::BRLOk:
|
|
|
516 case AVR::BRMIk:
|
|
|
517 case AVR::BRPLk:
|
|
|
518 case AVR::BRGEk:
|
|
|
519 case AVR::BRLTk:
|
|
|
520 return MI.getOperand(0).getMBB();
|
|
|
521 case AVR::BRBSsk:
|
|
|
522 case AVR::BRBCsk:
|
|
|
523 return MI.getOperand(1).getMBB();
|
|
|
524 case AVR::SBRCRrB:
|
|
|
525 case AVR::SBRSRrB:
|
|
|
526 case AVR::SBICAb:
|
|
|
527 case AVR::SBISAb:
|
|
|
528 llvm_unreachable("unimplemented branch instructions");
|
|
|
529 }
|
|
|
530 }
|
|
|
531
|
|
|
532 bool AVRInstrInfo::isBranchOffsetInRange(unsigned BranchOp,
|
|
|
533 int64_t BrOffset) const {
|
|
|
534
|
|
|
535 switch (BranchOp) {
|
|
|
536 default:
|
|
|
537 llvm_unreachable("unexpected opcode!");
|
|
|
538 case AVR::JMPk:
|
|
|
539 case AVR::CALLk:
|
|
|
540 return true;
|
|
|
541 case AVR::RCALLk:
|
|
|
542 case AVR::RJMPk:
|
|
|
543 return isIntN(13, BrOffset);
|
|
|
544 case AVR::BRBSsk:
|
|
|
545 case AVR::BRBCsk:
|
|
|
546 case AVR::BREQk:
|
|
|
547 case AVR::BRNEk:
|
|
|
548 case AVR::BRSHk:
|
|
|
549 case AVR::BRLOk:
|
|
|
550 case AVR::BRMIk:
|
|
|
551 case AVR::BRPLk:
|
|
|
552 case AVR::BRGEk:
|
|
|
553 case AVR::BRLTk:
|
|
|
554 return isIntN(7, BrOffset);
|
|
|
555 }
|
|
|
556 }
|
|
|
557
|
|
|
558 unsigned AVRInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
|
|
|
559 MachineBasicBlock &NewDestBB,
|
|
|
560 const DebugLoc &DL,
|
|
|
561 int64_t BrOffset,
|
|
|
562 RegScavenger *RS) const {
|
|
|
563 // This method inserts a *direct* branch (JMP), despite its name.
|
|
|
564 // LLVM calls this method to fixup unconditional branches; it never calls
|
|
|
565 // insertBranch or some hypothetical "insertDirectBranch".
|
|
|
566 // See lib/CodeGen/RegisterRelaxation.cpp for details.
|
|
|
567 // We end up here when a jump is too long for a RJMP instruction.
|
|
|
568 auto &MI = *BuildMI(&MBB, DL, get(AVR::JMPk)).addMBB(&NewDestBB);
|
|
|
569
|
|
|
570 return getInstSizeInBytes(MI);
|
|
|
571 }
|
|
|
572
|
|
120
|
573 } // end of namespace llvm
|
|
|
574
|
