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1 //===-- AVRInstrInfo.h - AVR Instruction Information ------------*- C++ -*-===//
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2 //
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3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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4 // See https://llvm.org/LICENSE.txt for license information.
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5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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6 //
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7 //===----------------------------------------------------------------------===//
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8 //
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9 // This file contains the AVR implementation of the TargetInstrInfo class.
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10 //
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11 //===----------------------------------------------------------------------===//
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12
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13 #ifndef LLVM_AVR_INSTR_INFO_H
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14 #define LLVM_AVR_INSTR_INFO_H
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15
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16 #include "llvm/CodeGen/TargetInstrInfo.h"
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17
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18 #include "AVRRegisterInfo.h"
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19
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20 #define GET_INSTRINFO_HEADER
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21 #include "AVRGenInstrInfo.inc"
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22 #undef GET_INSTRINFO_HEADER
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23
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24 namespace llvm {
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25
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26 namespace AVRCC {
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27
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28 /// AVR specific condition codes.
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29 /// These correspond to `AVR_*_COND` in `AVRInstrInfo.td`.
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30 /// They must be kept in synch.
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31 enum CondCodes {
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32 COND_EQ, //!< Equal
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33 COND_NE, //!< Not equal
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34 COND_GE, //!< Greater than or equal
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35 COND_LT, //!< Less than
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36 COND_SH, //!< Unsigned same or higher
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37 COND_LO, //!< Unsigned lower
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38 COND_MI, //!< Minus
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39 COND_PL, //!< Plus
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40 COND_INVALID
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41 };
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42
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43 } // end of namespace AVRCC
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44
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45 namespace AVRII {
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46
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47 /// Specifies a target operand flag.
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48 enum TOF {
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49 MO_NO_FLAG,
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50
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51 /// On a symbol operand, this represents the lo part.
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52 MO_LO = (1 << 1),
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53
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54 /// On a symbol operand, this represents the hi part.
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55 MO_HI = (1 << 2),
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56
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57 /// On a symbol operand, this represents it has to be negated.
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58 MO_NEG = (1 << 3)
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59 };
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60
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61 } // end of namespace AVRII
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62
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63 /// Utilities related to the AVR instruction set.
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64 class AVRInstrInfo : public AVRGenInstrInfo {
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65 public:
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66 explicit AVRInstrInfo();
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67
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68 const AVRRegisterInfo &getRegisterInfo() const { return RI; }
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69 const MCInstrDesc &getBrCond(AVRCC::CondCodes CC) const;
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70 AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
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71 AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const;
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72 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
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73
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74 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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75 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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76 bool KillSrc) const override;
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77 void storeRegToStackSlot(MachineBasicBlock &MBB,
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78 MachineBasicBlock::iterator MI, unsigned SrcReg,
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79 bool isKill, int FrameIndex,
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80 const TargetRegisterClass *RC,
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81 const TargetRegisterInfo *TRI) const override;
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82 void loadRegFromStackSlot(MachineBasicBlock &MBB,
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83 MachineBasicBlock::iterator MI, unsigned DestReg,
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84 int FrameIndex, const TargetRegisterClass *RC,
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85 const TargetRegisterInfo *TRI) const override;
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86 unsigned isLoadFromStackSlot(const MachineInstr &MI,
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87 int &FrameIndex) const override;
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88 unsigned isStoreToStackSlot(const MachineInstr &MI,
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89 int &FrameIndex) const override;
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90
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91 // Branch analysis.
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92 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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93 MachineBasicBlock *&FBB,
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94 SmallVectorImpl<MachineOperand> &Cond,
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95 bool AllowModify = false) const override;
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96 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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97 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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98 const DebugLoc &DL,
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99 int *BytesAdded = nullptr) const override;
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100 unsigned removeBranch(MachineBasicBlock &MBB,
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101 int *BytesRemoved = nullptr) const override;
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102 bool
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103 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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104
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105 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
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106
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107 bool isBranchOffsetInRange(unsigned BranchOpc,
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108 int64_t BrOffset) const override;
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109
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110 unsigned insertIndirectBranch(MachineBasicBlock &MBB,
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111 MachineBasicBlock &NewDestBB,
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112 const DebugLoc &DL,
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113 int64_t BrOffset,
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114 RegScavenger *RS) const override;
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120
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115 private:
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116 const AVRRegisterInfo RI;
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117 };
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118
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119 } // end namespace llvm
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120
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121 #endif // LLVM_AVR_INSTR_INFO_H
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