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1 //===- X86InstrVecCompiler.td - Vector Compiler Patterns ---*- tablegen -*-===//
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2 //
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3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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4 // See https://llvm.org/LICENSE.txt for license information.
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5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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121
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6 //
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7 //===----------------------------------------------------------------------===//
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8 //
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9 // This file describes the various vector pseudo instructions used by the
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10 // compiler, as well as Pat patterns used during instruction selection.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 //===----------------------------------------------------------------------===//
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15 // Non-instruction patterns
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16 //===----------------------------------------------------------------------===//
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17
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147
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18 let Predicates = [NoAVX512] in {
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19 // A vector extract of the first f32/f64 position is a subregister copy
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20 def : Pat<(f32 (extractelt (v4f32 VR128:$src), (iPTR 0))),
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21 (COPY_TO_REGCLASS (v4f32 VR128:$src), FR32)>;
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22 def : Pat<(f64 (extractelt (v2f64 VR128:$src), (iPTR 0))),
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23 (COPY_TO_REGCLASS (v2f64 VR128:$src), FR64)>;
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24 }
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25
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26 let Predicates = [HasAVX512] in {
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27 // A vector extract of the first f32/f64 position is a subregister copy
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28 def : Pat<(f32 (extractelt (v4f32 VR128X:$src), (iPTR 0))),
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29 (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X)>;
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30 def : Pat<(f64 (extractelt (v2f64 VR128X:$src), (iPTR 0))),
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31 (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X)>;
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32 }
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33
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147
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34 let Predicates = [NoVLX] in {
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35 // Implicitly promote a 32-bit scalar to a vector.
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36 def : Pat<(v4f32 (scalar_to_vector FR32:$src)),
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37 (COPY_TO_REGCLASS FR32:$src, VR128)>;
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38 // Implicitly promote a 64-bit scalar to a vector.
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39 def : Pat<(v2f64 (scalar_to_vector FR64:$src)),
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40 (COPY_TO_REGCLASS FR64:$src, VR128)>;
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41 }
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42
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147
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43 let Predicates = [HasVLX] in {
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44 // Implicitly promote a 32-bit scalar to a vector.
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45 def : Pat<(v4f32 (scalar_to_vector FR32X:$src)),
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46 (COPY_TO_REGCLASS FR32X:$src, VR128X)>;
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47 // Implicitly promote a 64-bit scalar to a vector.
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48 def : Pat<(v2f64 (scalar_to_vector FR64X:$src)),
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49 (COPY_TO_REGCLASS FR64X:$src, VR128X)>;
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50 }
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51
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52 //===----------------------------------------------------------------------===//
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53 // Subvector tricks
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54 //===----------------------------------------------------------------------===//
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55
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56 // Patterns for insert_subvector/extract_subvector to/from index=0
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57 multiclass subvector_subreg_lowering<RegisterClass subRC, ValueType subVT,
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58 RegisterClass RC, ValueType VT,
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59 SubRegIndex subIdx> {
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60 def : Pat<(subVT (extract_subvector (VT RC:$src), (iPTR 0))),
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61 (subVT (EXTRACT_SUBREG RC:$src, subIdx))>;
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62
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63 def : Pat<(VT (insert_subvector undef, subRC:$src, (iPTR 0))),
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64 (VT (INSERT_SUBREG (IMPLICIT_DEF), subRC:$src, subIdx))>;
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65 }
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66
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67 // A 128-bit subvector extract from the first 256-bit vector position is a
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68 // subregister copy that needs no instruction. Likewise, a 128-bit subvector
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69 // insert to the first 256-bit vector position is a subregister copy that needs
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70 // no instruction.
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71 defm : subvector_subreg_lowering<VR128, v4i32, VR256, v8i32, sub_xmm>;
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72 defm : subvector_subreg_lowering<VR128, v4f32, VR256, v8f32, sub_xmm>;
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73 defm : subvector_subreg_lowering<VR128, v2i64, VR256, v4i64, sub_xmm>;
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74 defm : subvector_subreg_lowering<VR128, v2f64, VR256, v4f64, sub_xmm>;
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75 defm : subvector_subreg_lowering<VR128, v8i16, VR256, v16i16, sub_xmm>;
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76 defm : subvector_subreg_lowering<VR128, v16i8, VR256, v32i8, sub_xmm>;
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77
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78 // A 128-bit subvector extract from the first 512-bit vector position is a
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79 // subregister copy that needs no instruction. Likewise, a 128-bit subvector
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80 // insert to the first 512-bit vector position is a subregister copy that needs
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81 // no instruction.
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82 defm : subvector_subreg_lowering<VR128, v4i32, VR512, v16i32, sub_xmm>;
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83 defm : subvector_subreg_lowering<VR128, v4f32, VR512, v16f32, sub_xmm>;
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84 defm : subvector_subreg_lowering<VR128, v2i64, VR512, v8i64, sub_xmm>;
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85 defm : subvector_subreg_lowering<VR128, v2f64, VR512, v8f64, sub_xmm>;
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86 defm : subvector_subreg_lowering<VR128, v8i16, VR512, v32i16, sub_xmm>;
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87 defm : subvector_subreg_lowering<VR128, v16i8, VR512, v64i8, sub_xmm>;
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88
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89 // A 128-bit subvector extract from the first 512-bit vector position is a
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90 // subregister copy that needs no instruction. Likewise, a 128-bit subvector
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91 // insert to the first 512-bit vector position is a subregister copy that needs
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92 // no instruction.
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93 defm : subvector_subreg_lowering<VR256, v8i32, VR512, v16i32, sub_ymm>;
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94 defm : subvector_subreg_lowering<VR256, v8f32, VR512, v16f32, sub_ymm>;
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95 defm : subvector_subreg_lowering<VR256, v4i64, VR512, v8i64, sub_ymm>;
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96 defm : subvector_subreg_lowering<VR256, v4f64, VR512, v8f64, sub_ymm>;
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97 defm : subvector_subreg_lowering<VR256, v16i16, VR512, v32i16, sub_ymm>;
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98 defm : subvector_subreg_lowering<VR256, v32i8, VR512, v64i8, sub_ymm>;
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99
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100
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101 // If we're inserting into an all zeros vector, just use a plain move which
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102 // will zero the upper bits. A post-isel hook will take care of removing
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103 // any moves that we can prove are unnecessary.
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104 multiclass subvec_zero_lowering<string MoveStr,
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105 RegisterClass RC, ValueType DstTy,
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106 ValueType SrcTy, ValueType ZeroTy,
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107 SubRegIndex SubIdx> {
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108 def : Pat<(DstTy (insert_subvector immAllZerosV,
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109 (SrcTy RC:$src), (iPTR 0))),
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110 (SUBREG_TO_REG (i64 0),
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111 (SrcTy (!cast<Instruction>("VMOV"#MoveStr#"rr") RC:$src)), SubIdx)>;
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121
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112 }
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113
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114 let Predicates = [HasAVX, NoVLX] in {
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115 defm : subvec_zero_lowering<"APD", VR128, v4f64, v2f64, v8i32, sub_xmm>;
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116 defm : subvec_zero_lowering<"APS", VR128, v8f32, v4f32, v8i32, sub_xmm>;
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117 defm : subvec_zero_lowering<"DQA", VR128, v4i64, v2i64, v8i32, sub_xmm>;
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118 defm : subvec_zero_lowering<"DQA", VR128, v8i32, v4i32, v8i32, sub_xmm>;
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119 defm : subvec_zero_lowering<"DQA", VR128, v16i16, v8i16, v8i32, sub_xmm>;
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120 defm : subvec_zero_lowering<"DQA", VR128, v32i8, v16i8, v8i32, sub_xmm>;
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121
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121 }
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122
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123 let Predicates = [HasVLX] in {
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124 defm : subvec_zero_lowering<"APDZ128", VR128X, v4f64, v2f64, v8i32, sub_xmm>;
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125 defm : subvec_zero_lowering<"APSZ128", VR128X, v8f32, v4f32, v8i32, sub_xmm>;
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126 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v4i64, v2i64, v8i32, sub_xmm>;
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127 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v8i32, v4i32, v8i32, sub_xmm>;
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128 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v16i16, v8i16, v8i32, sub_xmm>;
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129 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v32i8, v16i8, v8i32, sub_xmm>;
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130
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131 defm : subvec_zero_lowering<"APDZ128", VR128X, v8f64, v2f64, v16i32, sub_xmm>;
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132 defm : subvec_zero_lowering<"APSZ128", VR128X, v16f32, v4f32, v16i32, sub_xmm>;
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133 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v8i64, v2i64, v16i32, sub_xmm>;
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134 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v16i32, v4i32, v16i32, sub_xmm>;
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135 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v32i16, v8i16, v16i32, sub_xmm>;
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136 defm : subvec_zero_lowering<"DQA64Z128", VR128X, v64i8, v16i8, v16i32, sub_xmm>;
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137
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138 defm : subvec_zero_lowering<"APDZ256", VR256X, v8f64, v4f64, v16i32, sub_ymm>;
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139 defm : subvec_zero_lowering<"APSZ256", VR256X, v16f32, v8f32, v16i32, sub_ymm>;
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140 defm : subvec_zero_lowering<"DQA64Z256", VR256X, v8i64, v4i64, v16i32, sub_ymm>;
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141 defm : subvec_zero_lowering<"DQA64Z256", VR256X, v16i32, v8i32, v16i32, sub_ymm>;
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142 defm : subvec_zero_lowering<"DQA64Z256", VR256X, v32i16, v16i16, v16i32, sub_ymm>;
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143 defm : subvec_zero_lowering<"DQA64Z256", VR256X, v64i8, v32i8, v16i32, sub_ymm>;
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121
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144 }
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145
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146 let Predicates = [HasAVX512, NoVLX] in {
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147
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147 defm : subvec_zero_lowering<"APD", VR128, v8f64, v2f64, v16i32, sub_xmm>;
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148 defm : subvec_zero_lowering<"APS", VR128, v16f32, v4f32, v16i32, sub_xmm>;
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149 defm : subvec_zero_lowering<"DQA", VR128, v8i64, v2i64, v16i32, sub_xmm>;
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150 defm : subvec_zero_lowering<"DQA", VR128, v16i32, v4i32, v16i32, sub_xmm>;
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151 defm : subvec_zero_lowering<"DQA", VR128, v32i16, v8i16, v16i32, sub_xmm>;
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152 defm : subvec_zero_lowering<"DQA", VR128, v64i8, v16i8, v16i32, sub_xmm>;
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153
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154 defm : subvec_zero_lowering<"APDY", VR256, v8f64, v4f64, v16i32, sub_ymm>;
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155 defm : subvec_zero_lowering<"APSY", VR256, v16f32, v8f32, v16i32, sub_ymm>;
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156 defm : subvec_zero_lowering<"DQAY", VR256, v8i64, v4i64, v16i32, sub_ymm>;
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157 defm : subvec_zero_lowering<"DQAY", VR256, v16i32, v8i32, v16i32, sub_ymm>;
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158 defm : subvec_zero_lowering<"DQAY", VR256, v32i16, v16i16, v16i32, sub_ymm>;
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159 defm : subvec_zero_lowering<"DQAY", VR256, v64i8, v32i8, v16i32, sub_ymm>;
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121
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160 }
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161
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162 class maskzeroupper<ValueType vt, RegisterClass RC> :
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163 PatLeaf<(vt RC:$src), [{
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164 return isMaskZeroExtended(N);
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165 }]>;
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166
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167 def maskzeroupperv1i1 : maskzeroupper<v1i1, VK1>;
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168 def maskzeroupperv2i1 : maskzeroupper<v2i1, VK2>;
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169 def maskzeroupperv4i1 : maskzeroupper<v4i1, VK4>;
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170 def maskzeroupperv8i1 : maskzeroupper<v8i1, VK8>;
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171 def maskzeroupperv16i1 : maskzeroupper<v16i1, VK16>;
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172 def maskzeroupperv32i1 : maskzeroupper<v32i1, VK32>;
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173
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174 // The patterns determine if we can depend on the upper bits of a mask register
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175 // being zeroed by the previous operation so that we can skip explicit
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176 // zeroing.
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177 let Predicates = [HasBWI] in {
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178 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
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179 maskzeroupperv1i1:$src, (iPTR 0))),
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180 (COPY_TO_REGCLASS VK1:$src, VK32)>;
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181 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
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182 maskzeroupperv8i1:$src, (iPTR 0))),
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183 (COPY_TO_REGCLASS VK8:$src, VK32)>;
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184 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
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185 maskzeroupperv16i1:$src, (iPTR 0))),
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186 (COPY_TO_REGCLASS VK16:$src, VK32)>;
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187
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188 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
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189 maskzeroupperv1i1:$src, (iPTR 0))),
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190 (COPY_TO_REGCLASS VK1:$src, VK64)>;
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121
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191 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
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192 maskzeroupperv8i1:$src, (iPTR 0))),
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193 (COPY_TO_REGCLASS VK8:$src, VK64)>;
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194 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
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195 maskzeroupperv16i1:$src, (iPTR 0))),
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196 (COPY_TO_REGCLASS VK16:$src, VK64)>;
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197 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
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198 maskzeroupperv32i1:$src, (iPTR 0))),
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199 (COPY_TO_REGCLASS VK32:$src, VK64)>;
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200 }
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201
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202 let Predicates = [HasAVX512] in {
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203 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
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204 maskzeroupperv1i1:$src, (iPTR 0))),
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205 (COPY_TO_REGCLASS VK1:$src, VK16)>;
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206 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
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207 maskzeroupperv8i1:$src, (iPTR 0))),
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208 (COPY_TO_REGCLASS VK8:$src, VK16)>;
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209 }
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210
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211 let Predicates = [HasDQI] in {
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212 def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV),
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213 maskzeroupperv1i1:$src, (iPTR 0))),
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214 (COPY_TO_REGCLASS VK1:$src, VK8)>;
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215 }
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216
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134
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217 let Predicates = [HasVLX, HasDQI] in {
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121
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218 def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV),
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219 maskzeroupperv2i1:$src, (iPTR 0))),
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220 (COPY_TO_REGCLASS VK2:$src, VK8)>;
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221 def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV),
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222 maskzeroupperv4i1:$src, (iPTR 0))),
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223 (COPY_TO_REGCLASS VK4:$src, VK8)>;
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134
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224 }
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225
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226 let Predicates = [HasVLX] in {
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121
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227 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
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228 maskzeroupperv2i1:$src, (iPTR 0))),
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229 (COPY_TO_REGCLASS VK2:$src, VK16)>;
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230 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
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231 maskzeroupperv4i1:$src, (iPTR 0))),
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232 (COPY_TO_REGCLASS VK4:$src, VK16)>;
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233 }
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234
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235 let Predicates = [HasBWI, HasVLX] in {
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236 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
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237 maskzeroupperv2i1:$src, (iPTR 0))),
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238 (COPY_TO_REGCLASS VK2:$src, VK32)>;
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239 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
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240 maskzeroupperv4i1:$src, (iPTR 0))),
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241 (COPY_TO_REGCLASS VK4:$src, VK32)>;
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242 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
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243 maskzeroupperv2i1:$src, (iPTR 0))),
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244 (COPY_TO_REGCLASS VK2:$src, VK64)>;
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245 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
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246 maskzeroupperv4i1:$src, (iPTR 0))),
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247 (COPY_TO_REGCLASS VK4:$src, VK64)>;
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248 }
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249
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250 // If the bits are not zero we have to fall back to explicitly zeroing by
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251 // using shifts.
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134
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252 let Predicates = [HasAVX512] in {
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253 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
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254 (v1i1 VK1:$mask), (iPTR 0))),
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255 (KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK1:$mask, VK16),
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256 (i8 15)), (i8 15))>;
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257
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258 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
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259 (v2i1 VK2:$mask), (iPTR 0))),
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260 (KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK2:$mask, VK16),
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261 (i8 14)), (i8 14))>;
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262
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263 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
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264 (v4i1 VK4:$mask), (iPTR 0))),
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265 (KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK4:$mask, VK16),
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266 (i8 12)), (i8 12))>;
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267 }
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268
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269 let Predicates = [HasAVX512, NoDQI] in {
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121
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270 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
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271 (v8i1 VK8:$mask), (iPTR 0))),
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272 (KSHIFTRWri (KSHIFTLWri (COPY_TO_REGCLASS VK8:$mask, VK16),
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273 (i8 8)), (i8 8))>;
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274 }
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134
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275
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276 let Predicates = [HasDQI] in {
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277 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
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278 (v8i1 VK8:$mask), (iPTR 0))),
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279 (COPY_TO_REGCLASS (KMOVBkk VK8:$mask), VK16)>;
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280
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281 def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV),
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282 (v1i1 VK1:$mask), (iPTR 0))),
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283 (KSHIFTRBri (KSHIFTLBri (COPY_TO_REGCLASS VK1:$mask, VK8),
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284 (i8 7)), (i8 7))>;
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285 def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV),
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286 (v2i1 VK2:$mask), (iPTR 0))),
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287 (KSHIFTRBri (KSHIFTLBri (COPY_TO_REGCLASS VK2:$mask, VK8),
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288 (i8 6)), (i8 6))>;
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289 def : Pat<(v8i1 (insert_subvector (v8i1 immAllZerosV),
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290 (v4i1 VK4:$mask), (iPTR 0))),
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291 (KSHIFTRBri (KSHIFTLBri (COPY_TO_REGCLASS VK4:$mask, VK8),
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292 (i8 4)), (i8 4))>;
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293 }
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294
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295 let Predicates = [HasBWI] in {
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296 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
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297 (v16i1 VK16:$mask), (iPTR 0))),
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298 (COPY_TO_REGCLASS (KMOVWkk VK16:$mask), VK32)>;
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299
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300 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
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301 (v16i1 VK16:$mask), (iPTR 0))),
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302 (COPY_TO_REGCLASS (KMOVWkk VK16:$mask), VK64)>;
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303 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
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304 (v32i1 VK32:$mask), (iPTR 0))),
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305 (COPY_TO_REGCLASS (KMOVDkk VK32:$mask), VK64)>;
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306 }
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307
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308 let Predicates = [HasBWI, NoDQI] in {
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309 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
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310 (v8i1 VK8:$mask), (iPTR 0))),
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311 (KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK8:$mask, VK32),
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312 (i8 24)), (i8 24))>;
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313
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314 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
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315 (v8i1 VK8:$mask), (iPTR 0))),
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316 (KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK8:$mask, VK64),
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317 (i8 56)), (i8 56))>;
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318 }
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319
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320 let Predicates = [HasBWI, HasDQI] in {
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321 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
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322 (v8i1 VK8:$mask), (iPTR 0))),
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323 (COPY_TO_REGCLASS (KMOVBkk VK8:$mask), VK32)>;
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324
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325 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
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326 (v8i1 VK8:$mask), (iPTR 0))),
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327 (COPY_TO_REGCLASS (KMOVBkk VK8:$mask), VK64)>;
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328 }
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329
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147
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330 let Predicates = [HasBWI] in {
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134
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331 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
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332 (v1i1 VK1:$mask), (iPTR 0))),
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333 (KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK1:$mask, VK32),
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334 (i8 31)), (i8 31))>;
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335 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
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336 (v2i1 VK2:$mask), (iPTR 0))),
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337 (KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK2:$mask, VK32),
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338 (i8 30)), (i8 30))>;
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339 def : Pat<(v32i1 (insert_subvector (v32i1 immAllZerosV),
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340 (v4i1 VK4:$mask), (iPTR 0))),
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341 (KSHIFTRDri (KSHIFTLDri (COPY_TO_REGCLASS VK4:$mask, VK32),
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342 (i8 28)), (i8 28))>;
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343
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344 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
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345 (v1i1 VK1:$mask), (iPTR 0))),
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346 (KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK1:$mask, VK64),
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347 (i8 63)), (i8 63))>;
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348 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
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349 (v2i1 VK2:$mask), (iPTR 0))),
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350 (KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK2:$mask, VK64),
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351 (i8 62)), (i8 62))>;
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352 def : Pat<(v64i1 (insert_subvector (v64i1 immAllZerosV),
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353 (v4i1 VK4:$mask), (iPTR 0))),
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354 (KSHIFTRQri (KSHIFTLQri (COPY_TO_REGCLASS VK4:$mask, VK64),
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355 (i8 60)), (i8 60))>;
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356 }
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147
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357
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358 //===----------------------------------------------------------------------===//
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359 // Extra selection patterns for f128, f128mem
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360
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361 // movaps is shorter than movdqa. movaps is in SSE and movdqa is in SSE2.
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362 let Predicates = [NoAVX] in {
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363 def : Pat<(alignedstore (f128 VR128:$src), addr:$dst),
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364 (MOVAPSmr addr:$dst, VR128:$src)>;
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365 def : Pat<(store (f128 VR128:$src), addr:$dst),
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366 (MOVUPSmr addr:$dst, VR128:$src)>;
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367
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368 def : Pat<(alignedloadf128 addr:$src),
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369 (MOVAPSrm addr:$src)>;
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370 def : Pat<(loadf128 addr:$src),
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371 (MOVUPSrm addr:$src)>;
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372 }
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373
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374 let Predicates = [HasAVX, NoVLX] in {
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375 def : Pat<(alignedstore (f128 VR128:$src), addr:$dst),
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376 (VMOVAPSmr addr:$dst, VR128:$src)>;
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377 def : Pat<(store (f128 VR128:$src), addr:$dst),
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378 (VMOVUPSmr addr:$dst, VR128:$src)>;
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379
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380 def : Pat<(alignedloadf128 addr:$src),
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381 (VMOVAPSrm addr:$src)>;
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382 def : Pat<(loadf128 addr:$src),
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383 (VMOVUPSrm addr:$src)>;
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384 }
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385
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386 let Predicates = [HasVLX] in {
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387 def : Pat<(alignedstore (f128 VR128X:$src), addr:$dst),
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388 (VMOVAPSZ128mr addr:$dst, VR128X:$src)>;
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389 def : Pat<(store (f128 VR128X:$src), addr:$dst),
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390 (VMOVUPSZ128mr addr:$dst, VR128X:$src)>;
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391
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392 def : Pat<(alignedloadf128 addr:$src),
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393 (VMOVAPSZ128rm addr:$src)>;
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394 def : Pat<(loadf128 addr:$src),
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|
395 (VMOVUPSZ128rm addr:$src)>;
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396 }
|
|
|
397
|
|
|
398 let Predicates = [UseSSE1] in {
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|
|
399 // andps is shorter than andpd or pand. andps is SSE and andpd/pand are in SSE2
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|
|
400 def : Pat<(f128 (X86fand VR128:$src1, (memopf128 addr:$src2))),
|
|
|
401 (ANDPSrm VR128:$src1, f128mem:$src2)>;
|
|
|
402
|
|
|
403 def : Pat<(f128 (X86fand VR128:$src1, VR128:$src2)),
|
|
|
404 (ANDPSrr VR128:$src1, VR128:$src2)>;
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|
|
405
|
|
|
406 def : Pat<(f128 (X86for VR128:$src1, (memopf128 addr:$src2))),
|
|
|
407 (ORPSrm VR128:$src1, f128mem:$src2)>;
|
|
|
408
|
|
|
409 def : Pat<(f128 (X86for VR128:$src1, VR128:$src2)),
|
|
|
410 (ORPSrr VR128:$src1, VR128:$src2)>;
|
|
|
411
|
|
|
412 def : Pat<(f128 (X86fxor VR128:$src1, (memopf128 addr:$src2))),
|
|
|
413 (XORPSrm VR128:$src1, f128mem:$src2)>;
|
|
|
414
|
|
|
415 def : Pat<(f128 (X86fxor VR128:$src1, VR128:$src2)),
|
|
|
416 (XORPSrr VR128:$src1, VR128:$src2)>;
|
|
|
417 }
|
|
|
418
|
|
|
419 let Predicates = [HasAVX, NoVLX] in {
|
|
|
420 // andps is shorter than andpd or pand. andps is SSE and andpd/pand are in SSE2
|
|
|
421 def : Pat<(f128 (X86fand VR128:$src1, (loadf128 addr:$src2))),
|
|
|
422 (VANDPSrm VR128:$src1, f128mem:$src2)>;
|
|
|
423
|
|
|
424 def : Pat<(f128 (X86fand VR128:$src1, VR128:$src2)),
|
|
|
425 (VANDPSrr VR128:$src1, VR128:$src2)>;
|
|
|
426
|
|
|
427 def : Pat<(f128 (X86for VR128:$src1, (loadf128 addr:$src2))),
|
|
|
428 (VORPSrm VR128:$src1, f128mem:$src2)>;
|
|
|
429
|
|
|
430 def : Pat<(f128 (X86for VR128:$src1, VR128:$src2)),
|
|
|
431 (VORPSrr VR128:$src1, VR128:$src2)>;
|
|
|
432
|
|
|
433 def : Pat<(f128 (X86fxor VR128:$src1, (loadf128 addr:$src2))),
|
|
|
434 (VXORPSrm VR128:$src1, f128mem:$src2)>;
|
|
|
435
|
|
|
436 def : Pat<(f128 (X86fxor VR128:$src1, VR128:$src2)),
|
|
|
437 (VXORPSrr VR128:$src1, VR128:$src2)>;
|
|
|
438 }
|
|
|
439
|
|
|
440 let Predicates = [HasVLX] in {
|
|
|
441 // andps is shorter than andpd or pand. andps is SSE and andpd/pand are in SSE2
|
|
|
442 def : Pat<(f128 (X86fand VR128X:$src1, (loadf128 addr:$src2))),
|
|
|
443 (VANDPSZ128rm VR128X:$src1, f128mem:$src2)>;
|
|
|
444
|
|
|
445 def : Pat<(f128 (X86fand VR128X:$src1, VR128X:$src2)),
|
|
|
446 (VANDPSZ128rr VR128X:$src1, VR128X:$src2)>;
|
|
|
447
|
|
|
448 def : Pat<(f128 (X86for VR128X:$src1, (loadf128 addr:$src2))),
|
|
|
449 (VORPSZ128rm VR128X:$src1, f128mem:$src2)>;
|
|
|
450
|
|
|
451 def : Pat<(f128 (X86for VR128X:$src1, VR128X:$src2)),
|
|
|
452 (VORPSZ128rr VR128X:$src1, VR128X:$src2)>;
|
|
|
453
|
|
|
454 def : Pat<(f128 (X86fxor VR128X:$src1, (loadf128 addr:$src2))),
|
|
|
455 (VXORPSZ128rm VR128X:$src1, f128mem:$src2)>;
|
|
|
456
|
|
|
457 def : Pat<(f128 (X86fxor VR128X:$src1, VR128X:$src2)),
|
|
|
458 (VXORPSZ128rr VR128X:$src1, VR128X:$src2)>;
|
|
|
459 }
|
