Mercurial > hg > CbC > CbC_llvm
annotate utils/TableGen/FastISelEmitter.cpp @ 15:66597e792247
minor fix
author | Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> |
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date | Tue, 17 Sep 2013 21:32:34 +0900 |
parents | 9ad51c7bc036 |
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rev | line source |
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1 //===- FastISelEmitter.cpp - Generate an instruction selector -------------===// |
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2 // |
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3 // The LLVM Compiler Infrastructure |
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4 // |
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5 // This file is distributed under the University of Illinois Open Source |
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6 // License. See LICENSE.TXT for details. |
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7 // |
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8 //===----------------------------------------------------------------------===// |
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9 // |
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10 // This tablegen backend emits code for use by the "fast" instruction |
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11 // selection algorithm. See the comments at the top of |
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12 // lib/CodeGen/SelectionDAG/FastISel.cpp for background. |
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13 // |
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14 // This file scans through the target's tablegen instruction-info files |
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15 // and extracts instructions with obvious-looking patterns, and it emits |
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16 // code to look up these instructions by type and operator. |
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17 // |
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18 //===----------------------------------------------------------------------===// |
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19 |
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20 #include "CodeGenDAGPatterns.h" |
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21 #include "llvm/ADT/SmallString.h" |
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22 #include "llvm/Support/Debug.h" |
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23 #include "llvm/Support/ErrorHandling.h" |
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24 #include "llvm/TableGen/Error.h" |
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25 #include "llvm/TableGen/Record.h" |
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26 #include "llvm/TableGen/TableGenBackend.h" |
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27 using namespace llvm; |
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28 |
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29 |
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30 /// InstructionMemo - This class holds additional information about an |
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31 /// instruction needed to emit code for it. |
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32 /// |
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33 namespace { |
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34 struct InstructionMemo { |
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35 std::string Name; |
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36 const CodeGenRegisterClass *RC; |
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37 std::string SubRegNo; |
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38 std::vector<std::string>* PhysRegs; |
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39 }; |
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40 } // End anonymous namespace |
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41 |
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42 /// ImmPredicateSet - This uniques predicates (represented as a string) and |
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43 /// gives them unique (small) integer ID's that start at 0. |
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44 namespace { |
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45 class ImmPredicateSet { |
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46 DenseMap<TreePattern *, unsigned> ImmIDs; |
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47 std::vector<TreePredicateFn> PredsByName; |
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48 public: |
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49 |
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50 unsigned getIDFor(TreePredicateFn Pred) { |
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51 unsigned &Entry = ImmIDs[Pred.getOrigPatFragRecord()]; |
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52 if (Entry == 0) { |
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53 PredsByName.push_back(Pred); |
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54 Entry = PredsByName.size(); |
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55 } |
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56 return Entry-1; |
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57 } |
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58 |
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59 const TreePredicateFn &getPredicate(unsigned i) { |
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60 assert(i < PredsByName.size()); |
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61 return PredsByName[i]; |
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62 } |
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63 |
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64 typedef std::vector<TreePredicateFn>::const_iterator iterator; |
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65 iterator begin() const { return PredsByName.begin(); } |
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66 iterator end() const { return PredsByName.end(); } |
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67 |
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68 }; |
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69 } // End anonymous namespace |
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70 |
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71 /// OperandsSignature - This class holds a description of a list of operand |
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72 /// types. It has utility methods for emitting text based on the operands. |
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73 /// |
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74 namespace { |
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75 struct OperandsSignature { |
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76 class OpKind { |
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77 enum { OK_Reg, OK_FP, OK_Imm, OK_Invalid = -1 }; |
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78 char Repr; |
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79 public: |
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80 |
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81 OpKind() : Repr(OK_Invalid) {} |
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82 |
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83 bool operator<(OpKind RHS) const { return Repr < RHS.Repr; } |
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84 bool operator==(OpKind RHS) const { return Repr == RHS.Repr; } |
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85 |
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86 static OpKind getReg() { OpKind K; K.Repr = OK_Reg; return K; } |
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87 static OpKind getFP() { OpKind K; K.Repr = OK_FP; return K; } |
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88 static OpKind getImm(unsigned V) { |
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89 assert((unsigned)OK_Imm+V < 128 && |
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90 "Too many integer predicates for the 'Repr' char"); |
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91 OpKind K; K.Repr = OK_Imm+V; return K; |
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92 } |
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93 |
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94 bool isReg() const { return Repr == OK_Reg; } |
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95 bool isFP() const { return Repr == OK_FP; } |
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96 bool isImm() const { return Repr >= OK_Imm; } |
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97 |
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98 unsigned getImmCode() const { assert(isImm()); return Repr-OK_Imm; } |
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99 |
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100 void printManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates, |
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101 bool StripImmCodes) const { |
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102 if (isReg()) |
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103 OS << 'r'; |
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104 else if (isFP()) |
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105 OS << 'f'; |
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106 else { |
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107 OS << 'i'; |
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108 if (!StripImmCodes) |
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109 if (unsigned Code = getImmCode()) |
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110 OS << "_" << ImmPredicates.getPredicate(Code-1).getFnName(); |
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111 } |
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112 } |
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113 }; |
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114 |
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115 |
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116 SmallVector<OpKind, 3> Operands; |
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117 |
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118 bool operator<(const OperandsSignature &O) const { |
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119 return Operands < O.Operands; |
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120 } |
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121 bool operator==(const OperandsSignature &O) const { |
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122 return Operands == O.Operands; |
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123 } |
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124 |
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125 bool empty() const { return Operands.empty(); } |
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126 |
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127 bool hasAnyImmediateCodes() const { |
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128 for (unsigned i = 0, e = Operands.size(); i != e; ++i) |
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129 if (Operands[i].isImm() && Operands[i].getImmCode() != 0) |
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130 return true; |
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131 return false; |
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132 } |
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133 |
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134 /// getWithoutImmCodes - Return a copy of this with any immediate codes forced |
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135 /// to zero. |
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136 OperandsSignature getWithoutImmCodes() const { |
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137 OperandsSignature Result; |
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138 for (unsigned i = 0, e = Operands.size(); i != e; ++i) |
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139 if (!Operands[i].isImm()) |
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140 Result.Operands.push_back(Operands[i]); |
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141 else |
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142 Result.Operands.push_back(OpKind::getImm(0)); |
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143 return Result; |
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144 } |
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145 |
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146 void emitImmediatePredicate(raw_ostream &OS, ImmPredicateSet &ImmPredicates) { |
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147 bool EmittedAnything = false; |
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148 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { |
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149 if (!Operands[i].isImm()) continue; |
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150 |
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151 unsigned Code = Operands[i].getImmCode(); |
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152 if (Code == 0) continue; |
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153 |
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154 if (EmittedAnything) |
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155 OS << " &&\n "; |
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156 |
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157 TreePredicateFn PredFn = ImmPredicates.getPredicate(Code-1); |
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158 |
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159 // Emit the type check. |
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160 OS << "VT == " |
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161 << getEnumName(PredFn.getOrigPatFragRecord()->getTree(0)->getType(0)) |
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162 << " && "; |
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163 |
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164 |
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165 OS << PredFn.getFnName() << "(imm" << i <<')'; |
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166 EmittedAnything = true; |
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167 } |
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168 } |
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169 |
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170 /// initialize - Examine the given pattern and initialize the contents |
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171 /// of the Operands array accordingly. Return true if all the operands |
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172 /// are supported, false otherwise. |
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173 /// |
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174 bool initialize(TreePatternNode *InstPatNode, const CodeGenTarget &Target, |
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175 MVT::SimpleValueType VT, |
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176 ImmPredicateSet &ImmediatePredicates) { |
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177 if (InstPatNode->isLeaf()) |
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178 return false; |
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179 |
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180 if (InstPatNode->getOperator()->getName() == "imm") { |
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181 Operands.push_back(OpKind::getImm(0)); |
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182 return true; |
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183 } |
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184 |
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185 if (InstPatNode->getOperator()->getName() == "fpimm") { |
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186 Operands.push_back(OpKind::getFP()); |
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187 return true; |
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188 } |
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189 |
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190 const CodeGenRegisterClass *DstRC = 0; |
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191 |
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192 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) { |
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193 TreePatternNode *Op = InstPatNode->getChild(i); |
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194 |
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195 // Handle imm operands specially. |
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196 if (!Op->isLeaf() && Op->getOperator()->getName() == "imm") { |
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197 unsigned PredNo = 0; |
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198 if (!Op->getPredicateFns().empty()) { |
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199 TreePredicateFn PredFn = Op->getPredicateFns()[0]; |
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200 // If there is more than one predicate weighing in on this operand |
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201 // then we don't handle it. This doesn't typically happen for |
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202 // immediates anyway. |
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203 if (Op->getPredicateFns().size() > 1 || |
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204 !PredFn.isImmediatePattern()) |
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205 return false; |
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206 // Ignore any instruction with 'FastIselShouldIgnore', these are |
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207 // not needed and just bloat the fast instruction selector. For |
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208 // example, X86 doesn't need to generate code to match ADD16ri8 since |
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209 // ADD16ri will do just fine. |
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210 Record *Rec = PredFn.getOrigPatFragRecord()->getRecord(); |
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211 if (Rec->getValueAsBit("FastIselShouldIgnore")) |
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212 return false; |
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213 |
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214 PredNo = ImmediatePredicates.getIDFor(PredFn)+1; |
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215 } |
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216 |
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217 // Handle unmatched immediate sizes here. |
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218 //if (Op->getType(0) != VT) |
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219 // return false; |
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220 |
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221 Operands.push_back(OpKind::getImm(PredNo)); |
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222 continue; |
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223 } |
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224 |
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225 |
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226 // For now, filter out any operand with a predicate. |
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227 // For now, filter out any operand with multiple values. |
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228 if (!Op->getPredicateFns().empty() || Op->getNumTypes() != 1) |
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229 return false; |
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230 |
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231 if (!Op->isLeaf()) { |
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232 if (Op->getOperator()->getName() == "fpimm") { |
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233 Operands.push_back(OpKind::getFP()); |
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234 continue; |
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235 } |
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236 // For now, ignore other non-leaf nodes. |
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237 return false; |
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238 } |
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239 |
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240 assert(Op->hasTypeSet(0) && "Type infererence not done?"); |
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241 |
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242 // For now, all the operands must have the same type (if they aren't |
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243 // immediates). Note that this causes us to reject variable sized shifts |
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244 // on X86. |
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245 if (Op->getType(0) != VT) |
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246 return false; |
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247 |
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248 DefInit *OpDI = dyn_cast<DefInit>(Op->getLeafValue()); |
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249 if (!OpDI) |
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250 return false; |
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251 Record *OpLeafRec = OpDI->getDef(); |
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252 |
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253 // For now, the only other thing we accept is register operands. |
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254 const CodeGenRegisterClass *RC = 0; |
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255 if (OpLeafRec->isSubClassOf("RegisterOperand")) |
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256 OpLeafRec = OpLeafRec->getValueAsDef("RegClass"); |
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257 if (OpLeafRec->isSubClassOf("RegisterClass")) |
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258 RC = &Target.getRegisterClass(OpLeafRec); |
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259 else if (OpLeafRec->isSubClassOf("Register")) |
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260 RC = Target.getRegBank().getRegClassForRegister(OpLeafRec); |
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261 else |
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262 return false; |
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263 |
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264 // For now, this needs to be a register class of some sort. |
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265 if (!RC) |
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266 return false; |
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267 |
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268 // For now, all the operands must have the same register class or be |
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269 // a strict subclass of the destination. |
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270 if (DstRC) { |
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271 if (DstRC != RC && !DstRC->hasSubClass(RC)) |
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272 return false; |
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273 } else |
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274 DstRC = RC; |
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275 Operands.push_back(OpKind::getReg()); |
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276 } |
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277 return true; |
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278 } |
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279 |
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280 void PrintParameters(raw_ostream &OS) const { |
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281 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { |
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282 if (Operands[i].isReg()) { |
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283 OS << "unsigned Op" << i << ", bool Op" << i << "IsKill"; |
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284 } else if (Operands[i].isImm()) { |
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285 OS << "uint64_t imm" << i; |
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286 } else if (Operands[i].isFP()) { |
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287 OS << "const ConstantFP *f" << i; |
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288 } else { |
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289 llvm_unreachable("Unknown operand kind!"); |
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290 } |
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291 if (i + 1 != e) |
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292 OS << ", "; |
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293 } |
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294 } |
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295 |
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296 void PrintArguments(raw_ostream &OS, |
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297 const std::vector<std::string> &PR) const { |
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298 assert(PR.size() == Operands.size()); |
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299 bool PrintedArg = false; |
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300 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { |
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301 if (PR[i] != "") |
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302 // Implicit physical register operand. |
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303 continue; |
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304 |
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305 if (PrintedArg) |
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306 OS << ", "; |
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307 if (Operands[i].isReg()) { |
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308 OS << "Op" << i << ", Op" << i << "IsKill"; |
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309 PrintedArg = true; |
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310 } else if (Operands[i].isImm()) { |
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311 OS << "imm" << i; |
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312 PrintedArg = true; |
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313 } else if (Operands[i].isFP()) { |
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314 OS << "f" << i; |
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315 PrintedArg = true; |
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316 } else { |
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317 llvm_unreachable("Unknown operand kind!"); |
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318 } |
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319 } |
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320 } |
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321 |
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322 void PrintArguments(raw_ostream &OS) const { |
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323 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { |
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324 if (Operands[i].isReg()) { |
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325 OS << "Op" << i << ", Op" << i << "IsKill"; |
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326 } else if (Operands[i].isImm()) { |
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327 OS << "imm" << i; |
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328 } else if (Operands[i].isFP()) { |
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329 OS << "f" << i; |
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330 } else { |
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331 llvm_unreachable("Unknown operand kind!"); |
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332 } |
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333 if (i + 1 != e) |
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334 OS << ", "; |
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335 } |
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336 } |
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337 |
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338 |
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339 void PrintManglingSuffix(raw_ostream &OS, const std::vector<std::string> &PR, |
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340 ImmPredicateSet &ImmPredicates, |
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341 bool StripImmCodes = false) const { |
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342 for (unsigned i = 0, e = Operands.size(); i != e; ++i) { |
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343 if (PR[i] != "") |
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344 // Implicit physical register operand. e.g. Instruction::Mul expect to |
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345 // select to a binary op. On x86, mul may take a single operand with |
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346 // the other operand being implicit. We must emit something that looks |
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347 // like a binary instruction except for the very inner FastEmitInst_* |
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348 // call. |
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349 continue; |
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350 Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes); |
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351 } |
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352 } |
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353 |
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354 void PrintManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates, |
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355 bool StripImmCodes = false) const { |
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356 for (unsigned i = 0, e = Operands.size(); i != e; ++i) |
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357 Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes); |
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358 } |
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359 }; |
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360 } // End anonymous namespace |
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361 |
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362 namespace { |
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363 class FastISelMap { |
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364 typedef std::map<std::string, InstructionMemo> PredMap; |
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365 typedef std::map<MVT::SimpleValueType, PredMap> RetPredMap; |
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366 typedef std::map<MVT::SimpleValueType, RetPredMap> TypeRetPredMap; |
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367 typedef std::map<std::string, TypeRetPredMap> OpcodeTypeRetPredMap; |
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368 typedef std::map<OperandsSignature, OpcodeTypeRetPredMap> |
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369 OperandsOpcodeTypeRetPredMap; |
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370 |
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371 OperandsOpcodeTypeRetPredMap SimplePatterns; |
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372 |
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373 std::map<OperandsSignature, std::vector<OperandsSignature> > |
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374 SignaturesWithConstantForms; |
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375 |
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376 std::string InstNS; |
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377 ImmPredicateSet ImmediatePredicates; |
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378 public: |
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379 explicit FastISelMap(std::string InstNS); |
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380 |
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381 void collectPatterns(CodeGenDAGPatterns &CGP); |
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382 void printImmediatePredicates(raw_ostream &OS); |
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383 void printFunctionDefinitions(raw_ostream &OS); |
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384 }; |
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385 } // End anonymous namespace |
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386 |
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387 static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) { |
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388 return CGP.getSDNodeInfo(Op).getEnumName(); |
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389 } |
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390 |
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391 static std::string getLegalCName(std::string OpName) { |
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392 std::string::size_type pos = OpName.find("::"); |
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393 if (pos != std::string::npos) |
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394 OpName.replace(pos, 2, "_"); |
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395 return OpName; |
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396 } |
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397 |
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398 FastISelMap::FastISelMap(std::string instns) |
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399 : InstNS(instns) { |
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400 } |
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401 |
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402 static std::string PhyRegForNode(TreePatternNode *Op, |
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403 const CodeGenTarget &Target) { |
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404 std::string PhysReg; |
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405 |
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406 if (!Op->isLeaf()) |
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407 return PhysReg; |
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408 |
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409 Record *OpLeafRec = cast<DefInit>(Op->getLeafValue())->getDef(); |
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410 if (!OpLeafRec->isSubClassOf("Register")) |
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411 return PhysReg; |
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412 |
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413 PhysReg += cast<StringInit>(OpLeafRec->getValue("Namespace")->getValue()) |
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414 ->getValue(); |
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415 PhysReg += "::"; |
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416 PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName(); |
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417 return PhysReg; |
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418 } |
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419 |
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420 void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) { |
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421 const CodeGenTarget &Target = CGP.getTargetInfo(); |
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422 |
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423 // Determine the target's namespace name. |
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424 InstNS = Target.getInstNamespace() + "::"; |
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425 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!"); |
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426 |
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427 // Scan through all the patterns and record the simple ones. |
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428 for (CodeGenDAGPatterns::ptm_iterator I = CGP.ptm_begin(), |
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429 E = CGP.ptm_end(); I != E; ++I) { |
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430 const PatternToMatch &Pattern = *I; |
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431 |
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432 // For now, just look at Instructions, so that we don't have to worry |
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433 // about emitting multiple instructions for a pattern. |
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434 TreePatternNode *Dst = Pattern.getDstPattern(); |
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435 if (Dst->isLeaf()) continue; |
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436 Record *Op = Dst->getOperator(); |
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437 if (!Op->isSubClassOf("Instruction")) |
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438 continue; |
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439 CodeGenInstruction &II = CGP.getTargetInfo().getInstruction(Op); |
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440 if (II.Operands.empty()) |
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441 continue; |
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442 |
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443 // For now, ignore multi-instruction patterns. |
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444 bool MultiInsts = false; |
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445 for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) { |
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446 TreePatternNode *ChildOp = Dst->getChild(i); |
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447 if (ChildOp->isLeaf()) |
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448 continue; |
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449 if (ChildOp->getOperator()->isSubClassOf("Instruction")) { |
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450 MultiInsts = true; |
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451 break; |
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452 } |
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453 } |
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454 if (MultiInsts) |
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455 continue; |
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456 |
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457 // For now, ignore instructions where the first operand is not an |
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458 // output register. |
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459 const CodeGenRegisterClass *DstRC = 0; |
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460 std::string SubRegNo; |
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461 if (Op->getName() != "EXTRACT_SUBREG") { |
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462 Record *Op0Rec = II.Operands[0].Rec; |
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463 if (Op0Rec->isSubClassOf("RegisterOperand")) |
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464 Op0Rec = Op0Rec->getValueAsDef("RegClass"); |
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465 if (!Op0Rec->isSubClassOf("RegisterClass")) |
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466 continue; |
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467 DstRC = &Target.getRegisterClass(Op0Rec); |
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468 if (!DstRC) |
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469 continue; |
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470 } else { |
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471 // If this isn't a leaf, then continue since the register classes are |
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472 // a bit too complicated for now. |
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473 if (!Dst->getChild(1)->isLeaf()) continue; |
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474 |
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475 DefInit *SR = dyn_cast<DefInit>(Dst->getChild(1)->getLeafValue()); |
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476 if (SR) |
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477 SubRegNo = getQualifiedName(SR->getDef()); |
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478 else |
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479 SubRegNo = Dst->getChild(1)->getLeafValue()->getAsString(); |
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480 } |
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481 |
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482 // Inspect the pattern. |
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483 TreePatternNode *InstPatNode = Pattern.getSrcPattern(); |
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484 if (!InstPatNode) continue; |
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485 if (InstPatNode->isLeaf()) continue; |
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486 |
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487 // Ignore multiple result nodes for now. |
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488 if (InstPatNode->getNumTypes() > 1) continue; |
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489 |
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490 Record *InstPatOp = InstPatNode->getOperator(); |
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491 std::string OpcodeName = getOpcodeName(InstPatOp, CGP); |
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492 MVT::SimpleValueType RetVT = MVT::isVoid; |
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493 if (InstPatNode->getNumTypes()) RetVT = InstPatNode->getType(0); |
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494 MVT::SimpleValueType VT = RetVT; |
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495 if (InstPatNode->getNumChildren()) { |
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496 assert(InstPatNode->getChild(0)->getNumTypes() == 1); |
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497 VT = InstPatNode->getChild(0)->getType(0); |
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498 } |
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499 |
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500 // For now, filter out any instructions with predicates. |
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501 if (!InstPatNode->getPredicateFns().empty()) |
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502 continue; |
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503 |
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504 // Check all the operands. |
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505 OperandsSignature Operands; |
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506 if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates)) |
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507 continue; |
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508 |
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509 std::vector<std::string>* PhysRegInputs = new std::vector<std::string>(); |
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510 if (InstPatNode->getOperator()->getName() == "imm" || |
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511 InstPatNode->getOperator()->getName() == "fpimm") |
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512 PhysRegInputs->push_back(""); |
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513 else { |
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514 // Compute the PhysRegs used by the given pattern, and check that |
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515 // the mapping from the src to dst patterns is simple. |
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516 bool FoundNonSimplePattern = false; |
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517 unsigned DstIndex = 0; |
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518 for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) { |
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519 std::string PhysReg = PhyRegForNode(InstPatNode->getChild(i), Target); |
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520 if (PhysReg.empty()) { |
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521 if (DstIndex >= Dst->getNumChildren() || |
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522 Dst->getChild(DstIndex)->getName() != |
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523 InstPatNode->getChild(i)->getName()) { |
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524 FoundNonSimplePattern = true; |
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525 break; |
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526 } |
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527 ++DstIndex; |
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528 } |
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529 |
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530 PhysRegInputs->push_back(PhysReg); |
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531 } |
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532 |
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533 if (Op->getName() != "EXTRACT_SUBREG" && DstIndex < Dst->getNumChildren()) |
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534 FoundNonSimplePattern = true; |
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535 |
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536 if (FoundNonSimplePattern) |
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537 continue; |
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538 } |
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539 |
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540 // Get the predicate that guards this pattern. |
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541 std::string PredicateCheck = Pattern.getPredicateCheck(); |
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542 |
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543 // Ok, we found a pattern that we can handle. Remember it. |
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544 InstructionMemo Memo = { |
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545 Pattern.getDstPattern()->getOperator()->getName(), |
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546 DstRC, |
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547 SubRegNo, |
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548 PhysRegInputs |
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549 }; |
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550 |
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551 if (SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck)) |
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552 PrintFatalError(Pattern.getSrcRecord()->getLoc(), |
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553 "Duplicate record in FastISel table!"); |
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554 |
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555 SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo; |
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556 |
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557 // If any of the operands were immediates with predicates on them, strip |
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558 // them down to a signature that doesn't have predicates so that we can |
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559 // associate them with the stripped predicate version. |
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560 if (Operands.hasAnyImmediateCodes()) { |
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561 SignaturesWithConstantForms[Operands.getWithoutImmCodes()] |
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562 .push_back(Operands); |
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563 } |
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564 } |
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565 } |
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566 |
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567 void FastISelMap::printImmediatePredicates(raw_ostream &OS) { |
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568 if (ImmediatePredicates.begin() == ImmediatePredicates.end()) |
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569 return; |
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570 |
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571 OS << "\n// FastEmit Immediate Predicate functions.\n"; |
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572 for (ImmPredicateSet::iterator I = ImmediatePredicates.begin(), |
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573 E = ImmediatePredicates.end(); I != E; ++I) { |
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574 OS << "static bool " << I->getFnName() << "(int64_t Imm) {\n"; |
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575 OS << I->getImmediatePredicateCode() << "\n}\n"; |
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576 } |
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577 |
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578 OS << "\n\n"; |
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579 } |
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580 |
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581 |
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582 void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { |
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583 // Now emit code for all the patterns that we collected. |
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584 for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(), |
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585 OE = SimplePatterns.end(); OI != OE; ++OI) { |
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586 const OperandsSignature &Operands = OI->first; |
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587 const OpcodeTypeRetPredMap &OTM = OI->second; |
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588 |
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589 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end(); |
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590 I != E; ++I) { |
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591 const std::string &Opcode = I->first; |
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592 const TypeRetPredMap &TM = I->second; |
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593 |
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594 OS << "// FastEmit functions for " << Opcode << ".\n"; |
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595 OS << "\n"; |
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596 |
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597 // Emit one function for each opcode,type pair. |
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598 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end(); |
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599 TI != TE; ++TI) { |
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600 MVT::SimpleValueType VT = TI->first; |
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601 const RetPredMap &RM = TI->second; |
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602 if (RM.size() != 1) { |
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603 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end(); |
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604 RI != RE; ++RI) { |
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605 MVT::SimpleValueType RetVT = RI->first; |
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606 const PredMap &PM = RI->second; |
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607 bool HasPred = false; |
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608 |
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609 OS << "unsigned FastEmit_" |
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610 << getLegalCName(Opcode) |
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611 << "_" << getLegalCName(getName(VT)) |
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612 << "_" << getLegalCName(getName(RetVT)) << "_"; |
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613 Operands.PrintManglingSuffix(OS, ImmediatePredicates); |
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614 OS << "("; |
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615 Operands.PrintParameters(OS); |
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616 OS << ") {\n"; |
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617 |
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618 // Emit code for each possible instruction. There may be |
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619 // multiple if there are subtarget concerns. |
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620 for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); |
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621 PI != PE; ++PI) { |
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622 std::string PredicateCheck = PI->first; |
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623 const InstructionMemo &Memo = PI->second; |
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624 |
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625 if (PredicateCheck.empty()) { |
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626 assert(!HasPred && |
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627 "Multiple instructions match, at least one has " |
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628 "a predicate and at least one doesn't!"); |
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629 } else { |
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630 OS << " if (" + PredicateCheck + ") {\n"; |
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631 OS << " "; |
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632 HasPred = true; |
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633 } |
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634 |
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635 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) { |
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636 if ((*Memo.PhysRegs)[i] != "") |
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637 OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, " |
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638 << "TII.get(TargetOpcode::COPY), " |
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639 << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n"; |
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640 } |
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641 |
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642 OS << " return FastEmitInst_"; |
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643 if (Memo.SubRegNo.empty()) { |
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644 Operands.PrintManglingSuffix(OS, *Memo.PhysRegs, |
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645 ImmediatePredicates, true); |
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646 OS << "(" << InstNS << Memo.Name << ", "; |
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647 OS << "&" << InstNS << Memo.RC->getName() << "RegClass"; |
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648 if (!Operands.empty()) |
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649 OS << ", "; |
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650 Operands.PrintArguments(OS, *Memo.PhysRegs); |
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651 OS << ");\n"; |
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652 } else { |
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653 OS << "extractsubreg(" << getName(RetVT); |
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654 OS << ", Op0, Op0IsKill, " << Memo.SubRegNo << ");\n"; |
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655 } |
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656 |
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657 if (HasPred) |
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658 OS << " }\n"; |
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659 |
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660 } |
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661 // Return 0 if none of the predicates were satisfied. |
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662 if (HasPred) |
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663 OS << " return 0;\n"; |
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664 OS << "}\n"; |
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665 OS << "\n"; |
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666 } |
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667 |
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668 // Emit one function for the type that demultiplexes on return type. |
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669 OS << "unsigned FastEmit_" |
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670 << getLegalCName(Opcode) << "_" |
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671 << getLegalCName(getName(VT)) << "_"; |
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672 Operands.PrintManglingSuffix(OS, ImmediatePredicates); |
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673 OS << "(MVT RetVT"; |
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674 if (!Operands.empty()) |
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675 OS << ", "; |
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676 Operands.PrintParameters(OS); |
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677 OS << ") {\nswitch (RetVT.SimpleTy) {\n"; |
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678 for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end(); |
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679 RI != RE; ++RI) { |
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680 MVT::SimpleValueType RetVT = RI->first; |
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681 OS << " case " << getName(RetVT) << ": return FastEmit_" |
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682 << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT)) |
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683 << "_" << getLegalCName(getName(RetVT)) << "_"; |
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684 Operands.PrintManglingSuffix(OS, ImmediatePredicates); |
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685 OS << "("; |
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686 Operands.PrintArguments(OS); |
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687 OS << ");\n"; |
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688 } |
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689 OS << " default: return 0;\n}\n}\n\n"; |
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690 |
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691 } else { |
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692 // Non-variadic return type. |
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693 OS << "unsigned FastEmit_" |
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694 << getLegalCName(Opcode) << "_" |
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695 << getLegalCName(getName(VT)) << "_"; |
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696 Operands.PrintManglingSuffix(OS, ImmediatePredicates); |
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697 OS << "(MVT RetVT"; |
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698 if (!Operands.empty()) |
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699 OS << ", "; |
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700 Operands.PrintParameters(OS); |
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701 OS << ") {\n"; |
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702 |
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703 OS << " if (RetVT.SimpleTy != " << getName(RM.begin()->first) |
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704 << ")\n return 0;\n"; |
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705 |
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706 const PredMap &PM = RM.begin()->second; |
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707 bool HasPred = false; |
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708 |
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709 // Emit code for each possible instruction. There may be |
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710 // multiple if there are subtarget concerns. |
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711 for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE; |
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712 ++PI) { |
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713 std::string PredicateCheck = PI->first; |
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714 const InstructionMemo &Memo = PI->second; |
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715 |
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716 if (PredicateCheck.empty()) { |
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717 assert(!HasPred && |
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718 "Multiple instructions match, at least one has " |
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719 "a predicate and at least one doesn't!"); |
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720 } else { |
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721 OS << " if (" + PredicateCheck + ") {\n"; |
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722 OS << " "; |
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723 HasPred = true; |
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724 } |
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725 |
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parents:
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726 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) { |
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727 if ((*Memo.PhysRegs)[i] != "") |
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728 OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, " |
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729 << "TII.get(TargetOpcode::COPY), " |
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730 << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n"; |
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731 } |
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parents:
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732 |
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733 OS << " return FastEmitInst_"; |
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734 |
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735 if (Memo.SubRegNo.empty()) { |
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736 Operands.PrintManglingSuffix(OS, *Memo.PhysRegs, |
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737 ImmediatePredicates, true); |
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738 OS << "(" << InstNS << Memo.Name << ", "; |
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739 OS << "&" << InstNS << Memo.RC->getName() << "RegClass"; |
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740 if (!Operands.empty()) |
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741 OS << ", "; |
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742 Operands.PrintArguments(OS, *Memo.PhysRegs); |
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743 OS << ");\n"; |
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744 } else { |
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745 OS << "extractsubreg(RetVT, Op0, Op0IsKill, "; |
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746 OS << Memo.SubRegNo; |
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747 OS << ");\n"; |
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748 } |
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749 |
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750 if (HasPred) |
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751 OS << " }\n"; |
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|
752 } |
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parents:
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changeset
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753 |
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754 // Return 0 if none of the predicates were satisfied. |
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parents:
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755 if (HasPred) |
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756 OS << " return 0;\n"; |
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757 OS << "}\n"; |
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parents:
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758 OS << "\n"; |
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759 } |
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760 } |
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761 |
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parents:
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762 // Emit one function for the opcode that demultiplexes based on the type. |
9ad51c7bc036
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parents:
diff
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763 OS << "unsigned FastEmit_" |
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parents:
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764 << getLegalCName(Opcode) << "_"; |
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parents:
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765 Operands.PrintManglingSuffix(OS, ImmediatePredicates); |
9ad51c7bc036
1st commit. remove git dir and add all files.
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parents:
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766 OS << "(MVT VT, MVT RetVT"; |
9ad51c7bc036
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parents:
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changeset
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767 if (!Operands.empty()) |
9ad51c7bc036
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parents:
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768 OS << ", "; |
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1st commit. remove git dir and add all files.
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769 Operands.PrintParameters(OS); |
9ad51c7bc036
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parents:
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770 OS << ") {\n"; |
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parents:
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771 OS << " switch (VT.SimpleTy) {\n"; |
9ad51c7bc036
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772 for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end(); |
9ad51c7bc036
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parents:
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773 TI != TE; ++TI) { |
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1st commit. remove git dir and add all files.
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parents:
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774 MVT::SimpleValueType VT = TI->first; |
9ad51c7bc036
1st commit. remove git dir and add all files.
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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775 std::string TypeName = getName(VT); |
9ad51c7bc036
1st commit. remove git dir and add all files.
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parents:
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776 OS << " case " << TypeName << ": return FastEmit_" |
9ad51c7bc036
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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777 << getLegalCName(Opcode) << "_" << getLegalCName(TypeName) << "_"; |
9ad51c7bc036
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parents:
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778 Operands.PrintManglingSuffix(OS, ImmediatePredicates); |
9ad51c7bc036
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parents:
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779 OS << "(RetVT"; |
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parents:
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780 if (!Operands.empty()) |
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parents:
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781 OS << ", "; |
9ad51c7bc036
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parents:
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782 Operands.PrintArguments(OS); |
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parents:
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783 OS << ");\n"; |
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784 } |
9ad51c7bc036
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785 OS << " default: return 0;\n"; |
9ad51c7bc036
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parents:
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786 OS << " }\n"; |
9ad51c7bc036
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parents:
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787 OS << "}\n"; |
9ad51c7bc036
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788 OS << "\n"; |
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789 } |
9ad51c7bc036
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parents:
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changeset
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790 |
9ad51c7bc036
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parents:
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791 OS << "// Top-level FastEmit function.\n"; |
9ad51c7bc036
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792 OS << "\n"; |
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parents:
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793 |
9ad51c7bc036
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parents:
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794 // Emit one function for the operand signature that demultiplexes based |
9ad51c7bc036
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parents:
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795 // on opcode and type. |
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parents:
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796 OS << "unsigned FastEmit_"; |
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parents:
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797 Operands.PrintManglingSuffix(OS, ImmediatePredicates); |
9ad51c7bc036
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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changeset
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798 OS << "(MVT VT, MVT RetVT, unsigned Opcode"; |
9ad51c7bc036
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parents:
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799 if (!Operands.empty()) |
9ad51c7bc036
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800 OS << ", "; |
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801 Operands.PrintParameters(OS); |
9ad51c7bc036
1st commit. remove git dir and add all files.
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802 OS << ") {\n"; |
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parents:
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803 |
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parents:
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changeset
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804 // If there are any forms of this signature available that operand on |
9ad51c7bc036
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parents:
diff
changeset
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805 // constrained forms of the immediate (e.g. 32-bit sext immediate in a |
9ad51c7bc036
1st commit. remove git dir and add all files.
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parents:
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806 // 64-bit operand), check them first. |
9ad51c7bc036
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parents:
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|
807 |
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parents:
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|
808 std::map<OperandsSignature, std::vector<OperandsSignature> >::iterator MI |
9ad51c7bc036
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parents:
diff
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809 = SignaturesWithConstantForms.find(Operands); |
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parents:
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changeset
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810 if (MI != SignaturesWithConstantForms.end()) { |
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parents:
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811 // Unique any duplicates out of the list. |
9ad51c7bc036
1st commit. remove git dir and add all files.
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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812 std::sort(MI->second.begin(), MI->second.end()); |
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parents:
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813 MI->second.erase(std::unique(MI->second.begin(), MI->second.end()), |
9ad51c7bc036
1st commit. remove git dir and add all files.
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parents:
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814 MI->second.end()); |
9ad51c7bc036
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parents:
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815 |
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parents:
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816 // Check each in order it was seen. It would be nice to have a good |
9ad51c7bc036
1st commit. remove git dir and add all files.
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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817 // relative ordering between them, but we're not going for optimality |
9ad51c7bc036
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parents:
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818 // here. |
9ad51c7bc036
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parents:
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819 for (unsigned i = 0, e = MI->second.size(); i != e; ++i) { |
9ad51c7bc036
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parents:
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820 OS << " if ("; |
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821 MI->second[i].emitImmediatePredicate(OS, ImmediatePredicates); |
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parents:
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822 OS << ")\n if (unsigned Reg = FastEmit_"; |
9ad51c7bc036
1st commit. remove git dir and add all files.
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parents:
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823 MI->second[i].PrintManglingSuffix(OS, ImmediatePredicates); |
9ad51c7bc036
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parents:
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824 OS << "(VT, RetVT, Opcode"; |
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parents:
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825 if (!MI->second[i].empty()) |
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parents:
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826 OS << ", "; |
9ad51c7bc036
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parents:
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827 MI->second[i].PrintArguments(OS); |
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parents:
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828 OS << "))\n return Reg;\n\n"; |
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829 } |
9ad51c7bc036
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parents:
diff
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830 |
9ad51c7bc036
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parents:
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831 // Done with this, remove it. |
9ad51c7bc036
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parents:
diff
changeset
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832 SignaturesWithConstantForms.erase(MI); |
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parents:
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833 } |
9ad51c7bc036
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parents:
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834 |
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parents:
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835 OS << " switch (Opcode) {\n"; |
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parents:
diff
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836 for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end(); |
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1st commit. remove git dir and add all files.
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837 I != E; ++I) { |
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parents:
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838 const std::string &Opcode = I->first; |
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parents:
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839 |
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parents:
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840 OS << " case " << Opcode << ": return FastEmit_" |
9ad51c7bc036
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parents:
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841 << getLegalCName(Opcode) << "_"; |
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parents:
diff
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842 Operands.PrintManglingSuffix(OS, ImmediatePredicates); |
9ad51c7bc036
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parents:
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changeset
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843 OS << "(VT, RetVT"; |
9ad51c7bc036
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parents:
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844 if (!Operands.empty()) |
9ad51c7bc036
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845 OS << ", "; |
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parents:
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846 Operands.PrintArguments(OS); |
9ad51c7bc036
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parents:
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847 OS << ");\n"; |
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848 } |
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849 OS << " default: return 0;\n"; |
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850 OS << " }\n"; |
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851 OS << "}\n"; |
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parents:
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852 OS << "\n"; |
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853 } |
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parents:
diff
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854 |
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parents:
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855 // TODO: SignaturesWithConstantForms should be empty here. |
9ad51c7bc036
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parents:
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changeset
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856 } |
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857 |
9ad51c7bc036
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parents:
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858 namespace llvm { |
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parents:
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859 |
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860 void EmitFastISel(RecordKeeper &RK, raw_ostream &OS) { |
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861 CodeGenDAGPatterns CGP(RK); |
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862 const CodeGenTarget &Target = CGP.getTargetInfo(); |
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863 emitSourceFileHeader("\"Fast\" Instruction Selector for the " + |
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864 Target.getName() + " target", OS); |
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865 |
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866 // Determine the target's namespace name. |
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867 std::string InstNS = Target.getInstNamespace() + "::"; |
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868 assert(InstNS.size() > 2 && "Can't determine target-specific namespace!"); |
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869 |
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870 FastISelMap F(InstNS); |
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871 F.collectPatterns(CGP); |
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872 F.printImmediatePredicates(OS); |
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873 F.printFunctionDefinitions(OS); |
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874 } |
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875 |
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876 } // End llvm namespace |