annotate docs/HistoricalNotes/2003-06-26-Reoptimizer2.txt @ 136:6cd7e602c98b

Fix compile error to update llvm 5.0.1
author mir3636
date Sat, 17 Feb 2018 11:50:31 +0900
parents 95c75e76d11b
children
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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1 Thu Jun 26 14:43:04 CDT 2003
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2
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3 Information about BinInterface
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4 ------------------------------
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5
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6 Take in a set of instructions with some particular register
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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7 allocation. It allows you to add, modify, or delete some instructions,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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8 in SSA form (kind of like LLVM's MachineInstrs.) Then re-allocate
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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9 registers. It assumes that the transformations you are doing are safe.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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10 It does not update the mapping information or the LLVM representation
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11 for the modified trace (so it would not, for instance, support
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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12 multiple optimization passes; passes have to be aware of and update
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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13 manually the mapping information.)
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14
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15 The way you use it is you take the original code and provide it to
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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16 BinInterface; then you do optimizations to it, then you put it in the
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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17 trace cache.
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18
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19 The BinInterface tries to find live-outs for traces so that it can do
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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20 register allocation on just the trace, and stitch the trace back into
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21 the original code. It has to preserve the live-ins and live-outs when
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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22 it does its register allocation. (On exits from the trace we have
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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23 epilogues that copy live-outs back into the right registers, but
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24 live-ins have to be in the right registers.)
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25
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26
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27 Limitations of BinInterface
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28 ---------------------------
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29
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30 It does copy insertions for PHIs, which it infers from the machine
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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31 code. The mapping info inserted by LLC is not sufficient to determine
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32 the PHIs.
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33
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34 It does not handle integer or floating-point condition codes and it
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35 does not handle floating-point register allocation.
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36
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37 It is not aggressively able to use lots of registers.
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38
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39 There is a problem with alloca: we cannot find our spill space for
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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40 spilling registers, normally allocated on the stack, if the trace
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41 follows an alloca(). What might be an acceptable solution would be to
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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42 disable trace generation on functions that have variable-sized
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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43 alloca()s. Variable-sized allocas in the trace would also probably
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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44 screw things up.
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45
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46 Because of the FP and alloca limitations, the BinInterface is
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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47 completely disabled right now.
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48
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49
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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50 Demo
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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51 ----
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52
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53 This is a demo of the Ball & Larus version that does NOT use 2-level
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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54 profiling.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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55
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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56 1. Compile program with llvm-gcc.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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57 2. Run opt -lowerswitch -paths -emitfuncs on the bytecode.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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58 -lowerswitch change switch statements to branches
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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59 -paths Ball & Larus path-profiling algorithm
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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60 -emitfuncs emit the table of functions
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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61 3. Run llc to generate SPARC assembly code for the result of step 2.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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62 4. Use g++ to link the (instrumented) assembly code.
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63
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64 We use a script to do all this:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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65 ------------------------------------------------------------------------------
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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66 #!/bin/sh
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67 llvm-gcc $1.c -o $1
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68 opt -lowerswitch -paths -emitfuncs $1.bc > $1.run.bc
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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69 llc -f $1.run.bc
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70 LIBS=$HOME/llvm_sparc/lib/Debug
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71 GXX=/usr/dcs/software/evaluation/bin/g++
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72 $GXX -g -L $LIBS $1.run.s -o $1.run.llc \
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73 $LIBS/tracecache.o \
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74 $LIBS/mapinfo.o \
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75 $LIBS/trigger.o \
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76 $LIBS/profpaths.o \
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77 $LIBS/bininterface.o \
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78 $LIBS/support.o \
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79 $LIBS/vmcore.o \
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80 $LIBS/transformutils.o \
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81 $LIBS/bcreader.o \
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82 -lscalaropts -lscalaropts -lanalysis \
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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83 -lmalloc -lcpc -lm -ldl
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84 ------------------------------------------------------------------------------
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85
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86 5. Run the resulting binary. You will see output from BinInterface
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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87 (described below) intermixed with the output from the program.
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88
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89
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90 Output from BinInterface
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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91 ------------------------
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92
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93 BinInterface's debugging code prints out the following stuff in order:
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94
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95 1. Initial code provided to BinInterface with original register
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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96 allocation.
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97
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98 2. Section 0 is the trace prolog, consisting mainly of live-ins and
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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99 register saves which will be restored in epilogs.
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100
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101 3. Section 1 is the trace itself, in SSA form used by BinInterface,
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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102 along with the PHIs that are inserted.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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103 PHIs are followed by the copies that implement them.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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104 Each branch (i.e., out of the trace) is annotated with the
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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105 section number that represents the epilog it branches to.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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106
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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107 4. All the other sections starting with Section 2 are trace epilogs.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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108 Every branch from the trace has to go to some epilog.
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109
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110 5. After the last section is the register allocation output.