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150
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1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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221
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2 ; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX9 %s
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3 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=VI %s
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4 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=CI %s
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5 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GFX10 %s
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150
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6
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7 define amdgpu_kernel void @s_shl_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> %lhs, <2 x i16> %rhs) #0 {
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8 ; GFX9-LABEL: s_shl_v2i16:
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9 ; GFX9: ; %bb.0:
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10 ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
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11 ; GFX9-NEXT: s_load_dword s2, s[0:1], 0x2c
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221
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12 ; GFX9-NEXT: s_load_dword s3, s[0:1], 0x30
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150
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13 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
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14 ; GFX9-NEXT: s_mov_b32 s6, -1
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15 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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16 ; GFX9-NEXT: v_mov_b32_e32 v0, s2
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221
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17 ; GFX9-NEXT: v_pk_lshlrev_b16 v0, s3, v0
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150
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18 ; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0
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19 ; GFX9-NEXT: s_endpgm
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20 ;
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21 ; VI-LABEL: s_shl_v2i16:
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22 ; VI: ; %bb.0:
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23 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
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24 ; VI-NEXT: s_load_dword s2, s[0:1], 0x2c
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25 ; VI-NEXT: s_load_dword s0, s[0:1], 0x30
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26 ; VI-NEXT: s_mov_b32 s3, 0xffff
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27 ; VI-NEXT: s_mov_b32 s7, 0xf000
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28 ; VI-NEXT: s_mov_b32 s6, -1
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29 ; VI-NEXT: s_waitcnt lgkmcnt(0)
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30 ; VI-NEXT: s_lshr_b32 s1, s2, 16
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31 ; VI-NEXT: s_lshr_b32 s8, s0, 16
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32 ; VI-NEXT: s_and_b32 s2, s2, s3
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33 ; VI-NEXT: s_and_b32 s0, s0, s3
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34 ; VI-NEXT: s_lshl_b32 s0, s2, s0
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35 ; VI-NEXT: s_lshl_b32 s1, s1, s8
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36 ; VI-NEXT: s_lshl_b32 s1, s1, 16
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37 ; VI-NEXT: s_and_b32 s0, s0, s3
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38 ; VI-NEXT: s_or_b32 s0, s0, s1
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39 ; VI-NEXT: v_mov_b32_e32 v0, s0
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40 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
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41 ; VI-NEXT: s_endpgm
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42 ;
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43 ; CI-LABEL: s_shl_v2i16:
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44 ; CI: ; %bb.0:
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45 ; CI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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46 ; CI-NEXT: s_load_dword s2, s[0:1], 0xb
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47 ; CI-NEXT: s_load_dword s0, s[0:1], 0xc
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48 ; CI-NEXT: s_mov_b32 s3, 0xffff
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49 ; CI-NEXT: s_mov_b32 s7, 0xf000
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50 ; CI-NEXT: s_mov_b32 s6, -1
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51 ; CI-NEXT: s_waitcnt lgkmcnt(0)
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52 ; CI-NEXT: s_lshr_b32 s1, s2, 16
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53 ; CI-NEXT: s_and_b32 s8, s0, s3
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54 ; CI-NEXT: s_lshr_b32 s0, s0, 16
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55 ; CI-NEXT: s_lshl_b32 s0, s1, s0
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56 ; CI-NEXT: s_lshl_b32 s1, s2, s8
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57 ; CI-NEXT: s_lshl_b32 s0, s0, 16
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58 ; CI-NEXT: s_and_b32 s1, s1, s3
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59 ; CI-NEXT: s_or_b32 s0, s1, s0
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60 ; CI-NEXT: v_mov_b32_e32 v0, s0
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61 ; CI-NEXT: buffer_store_dword v0, off, s[4:7], 0
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62 ; CI-NEXT: s_endpgm
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221
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63 ;
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64 ; GFX10-LABEL: s_shl_v2i16:
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65 ; GFX10: ; %bb.0:
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66 ; GFX10-NEXT: s_clause 0x2
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67 ; GFX10-NEXT: s_load_dword s2, s[0:1], 0x2c
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68 ; GFX10-NEXT: s_load_dword s3, s[0:1], 0x30
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69 ; GFX10-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
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70 ; GFX10-NEXT: s_mov_b32 s7, 0x31016000
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71 ; GFX10-NEXT: s_mov_b32 s6, -1
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72 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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73 ; GFX10-NEXT: v_pk_lshlrev_b16 v0, s3, s2
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74 ; GFX10-NEXT: buffer_store_dword v0, off, s[4:7], 0
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75 ; GFX10-NEXT: s_endpgm
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150
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76 %result = shl <2 x i16> %lhs, %rhs
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77 store <2 x i16> %result, <2 x i16> addrspace(1)* %out
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78 ret void
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79 }
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80
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81 define amdgpu_kernel void @v_shl_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
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82 ; GFX9-LABEL: v_shl_v2i16:
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83 ; GFX9: ; %bb.0:
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84 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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221
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85 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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150
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86 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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221
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87 ; GFX9-NEXT: global_load_dword v1, v0, s[2:3]
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88 ; GFX9-NEXT: global_load_dword v2, v0, s[2:3] offset:4
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150
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89 ; GFX9-NEXT: s_waitcnt vmcnt(0)
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221
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90 ; GFX9-NEXT: v_pk_lshlrev_b16 v1, v2, v1
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91 ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
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150
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92 ; GFX9-NEXT: s_endpgm
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93 ;
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94 ; VI-LABEL: v_shl_v2i16:
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95 ; VI: ; %bb.0:
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96 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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221
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97 ; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
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150
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98 ; VI-NEXT: s_waitcnt lgkmcnt(0)
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99 ; VI-NEXT: v_mov_b32_e32 v1, s3
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221
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100 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
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150
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101 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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221
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102 ; VI-NEXT: v_add_u32_e32 v2, vcc, 4, v0
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103 ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
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104 ; VI-NEXT: flat_load_dword v5, v[0:1]
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105 ; VI-NEXT: flat_load_dword v2, v[2:3]
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106 ; VI-NEXT: v_mov_b32_e32 v1, s1
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107 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v4
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108 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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109 ; VI-NEXT: s_waitcnt vmcnt(0)
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110 ; VI-NEXT: v_lshlrev_b16_e32 v3, v2, v5
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111 ; VI-NEXT: v_lshlrev_b16_sdwa v2, v2, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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112 ; VI-NEXT: v_or_b32_e32 v2, v3, v2
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113 ; VI-NEXT: flat_store_dword v[0:1], v2
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150
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114 ; VI-NEXT: s_endpgm
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115 ;
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116 ; CI-LABEL: v_shl_v2i16:
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117 ; CI: ; %bb.0:
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173
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118 ; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
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119 ; CI-NEXT: s_mov_b32 s3, 0xf000
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120 ; CI-NEXT: s_mov_b32 s2, 0
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150
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121 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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122 ; CI-NEXT: v_mov_b32_e32 v1, 0
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123 ; CI-NEXT: s_waitcnt lgkmcnt(0)
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173
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124 ; CI-NEXT: s_mov_b64 s[0:1], s[6:7]
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125 ; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64
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126 ; CI-NEXT: buffer_load_dword v3, v[0:1], s[0:3], 0 addr64 offset:4
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221
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127 ; CI-NEXT: s_mov_b32 s0, 0xffff
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173
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128 ; CI-NEXT: s_mov_b64 s[6:7], s[2:3]
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150
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129 ; CI-NEXT: s_waitcnt vmcnt(1)
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130 ; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v2
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131 ; CI-NEXT: s_waitcnt vmcnt(0)
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221
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132 ; CI-NEXT: v_and_b32_e32 v5, s0, v3
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150
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133 ; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
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134 ; CI-NEXT: v_lshl_b32_e32 v3, v4, v3
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135 ; CI-NEXT: v_lshl_b32_e32 v2, v2, v5
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136 ; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
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221
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137 ; CI-NEXT: v_and_b32_e32 v2, s0, v2
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150
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138 ; CI-NEXT: v_or_b32_e32 v2, v2, v3
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173
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139 ; CI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
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150
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140 ; CI-NEXT: s_endpgm
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221
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141 ;
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142 ; GFX10-LABEL: v_shl_v2i16:
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143 ; GFX10: ; %bb.0:
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144 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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145 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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146 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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147 ; GFX10-NEXT: s_clause 0x1
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148 ; GFX10-NEXT: global_load_dword v1, v0, s[2:3]
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149 ; GFX10-NEXT: global_load_dword v2, v0, s[2:3] offset:4
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150 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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151 ; GFX10-NEXT: v_pk_lshlrev_b16 v1, v2, v1
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152 ; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
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153 ; GFX10-NEXT: s_endpgm
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150
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154 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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155 %tid.ext = sext i32 %tid to i64
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156 %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
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157 %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
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158 %b_ptr = getelementptr <2 x i16>, <2 x i16> addrspace(1)* %in.gep, i32 1
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159 %a = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
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160 %b = load <2 x i16>, <2 x i16> addrspace(1)* %b_ptr
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161 %result = shl <2 x i16> %a, %b
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162 store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
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163 ret void
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164 }
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165
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166 define amdgpu_kernel void @shl_v_s_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in, <2 x i16> %sgpr) #0 {
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167 ; GFX9-LABEL: shl_v_s_v2i16:
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168 ; GFX9: ; %bb.0:
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169 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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221
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170 ; GFX9-NEXT: s_load_dword s2, s[0:1], 0x34
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171 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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150
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172 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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221
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173 ; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
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150
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174 ; GFX9-NEXT: s_waitcnt vmcnt(0)
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221
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175 ; GFX9-NEXT: v_pk_lshlrev_b16 v1, s2, v1
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176 ; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
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150
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177 ; GFX9-NEXT: s_endpgm
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178 ;
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179 ; VI-LABEL: shl_v_s_v2i16:
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180 ; VI: ; %bb.0:
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181 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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182 ; VI-NEXT: s_load_dword s0, s[0:1], 0x34
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183 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
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184 ; VI-NEXT: s_waitcnt lgkmcnt(0)
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185 ; VI-NEXT: v_mov_b32_e32 v1, s7
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186 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2
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187 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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221
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188 ; VI-NEXT: flat_load_dword v3, v[0:1]
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150
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189 ; VI-NEXT: s_lshr_b32 s1, s0, 16
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221
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190 ; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v2
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191 ; VI-NEXT: v_mov_b32_e32 v2, s1
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192 ; VI-NEXT: v_mov_b32_e32 v1, s5
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193 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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194 ; VI-NEXT: s_waitcnt vmcnt(0)
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195 ; VI-NEXT: v_lshlrev_b16_e32 v4, s0, v3
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196 ; VI-NEXT: v_lshlrev_b16_sdwa v2, v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
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197 ; VI-NEXT: v_or_b32_e32 v2, v4, v2
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198 ; VI-NEXT: flat_store_dword v[0:1], v2
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150
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199 ; VI-NEXT: s_endpgm
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200 ;
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201 ; CI-LABEL: shl_v_s_v2i16:
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202 ; CI: ; %bb.0:
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203 ; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
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221
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204 ; CI-NEXT: s_load_dword s8, s[0:1], 0xd
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150
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205 ; CI-NEXT: s_mov_b32 s3, 0xf000
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206 ; CI-NEXT: s_mov_b32 s2, 0
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207 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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208 ; CI-NEXT: s_waitcnt lgkmcnt(0)
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209 ; CI-NEXT: s_mov_b64 s[0:1], s[6:7]
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210 ; CI-NEXT: v_mov_b32_e32 v1, 0
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211 ; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64
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221
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212 ; CI-NEXT: s_mov_b32 s0, 0xffff
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213 ; CI-NEXT: s_lshr_b32 s1, s8, 16
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214 ; CI-NEXT: s_and_b32 s8, s8, s0
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150
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215 ; CI-NEXT: s_mov_b64 s[6:7], s[2:3]
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216 ; CI-NEXT: s_waitcnt vmcnt(0)
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217 ; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
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221
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218 ; CI-NEXT: v_lshlrev_b32_e32 v2, s8, v2
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219 ; CI-NEXT: v_lshlrev_b32_e32 v3, s1, v3
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220 ; CI-NEXT: v_and_b32_e32 v2, s0, v2
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150
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221 ; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3
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222 ; CI-NEXT: v_or_b32_e32 v2, v2, v3
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223 ; CI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
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224 ; CI-NEXT: s_endpgm
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221
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225 ;
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226 ; GFX10-LABEL: shl_v_s_v2i16:
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227 ; GFX10: ; %bb.0:
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228 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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229 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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230 ; GFX10-NEXT: s_load_dword s0, s[0:1], 0x34
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231 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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232 ; GFX10-NEXT: global_load_dword v1, v0, s[6:7]
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233 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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234 ; GFX10-NEXT: v_pk_lshlrev_b16 v1, s0, v1
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235 ; GFX10-NEXT: global_store_dword v0, v1, s[4:5]
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236 ; GFX10-NEXT: s_endpgm
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150
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237 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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238 %tid.ext = sext i32 %tid to i64
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239 %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
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240 %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
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241 %vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
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242 %result = shl <2 x i16> %vgpr, %sgpr
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243 store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
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244 ret void
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245 }
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246
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247 define amdgpu_kernel void @shl_s_v_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in, <2 x i16> %sgpr) #0 {
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248 ; GFX9-LABEL: shl_s_v_v2i16:
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249 ; GFX9: ; %bb.0:
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250 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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221
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251 ; GFX9-NEXT: s_load_dword s2, s[0:1], 0x34
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252 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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150
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253 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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221
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254 ; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
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150
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255 ; GFX9-NEXT: s_waitcnt vmcnt(0)
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221
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256 ; GFX9-NEXT: v_pk_lshlrev_b16 v1, v1, s2
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257 ; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
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150
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258 ; GFX9-NEXT: s_endpgm
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259 ;
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260 ; VI-LABEL: shl_s_v_v2i16:
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261 ; VI: ; %bb.0:
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262 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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263 ; VI-NEXT: s_load_dword s0, s[0:1], 0x34
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264 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
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265 ; VI-NEXT: s_waitcnt lgkmcnt(0)
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266 ; VI-NEXT: v_mov_b32_e32 v1, s7
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267 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2
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268 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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221
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269 ; VI-NEXT: flat_load_dword v3, v[0:1]
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150
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270 ; VI-NEXT: s_lshr_b32 s1, s0, 16
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221
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271 ; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v2
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272 ; VI-NEXT: v_mov_b32_e32 v2, s1
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273 ; VI-NEXT: v_mov_b32_e32 v1, s5
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274 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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275 ; VI-NEXT: s_waitcnt vmcnt(0)
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276 ; VI-NEXT: v_lshlrev_b16_e64 v4, v3, s0
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277 ; VI-NEXT: v_lshlrev_b16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
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278 ; VI-NEXT: v_or_b32_e32 v2, v4, v2
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279 ; VI-NEXT: flat_store_dword v[0:1], v2
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150
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280 ; VI-NEXT: s_endpgm
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281 ;
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282 ; CI-LABEL: shl_s_v_v2i16:
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283 ; CI: ; %bb.0:
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284 ; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
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285 ; CI-NEXT: s_load_dword s8, s[0:1], 0xd
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286 ; CI-NEXT: s_mov_b32 s3, 0xf000
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287 ; CI-NEXT: s_mov_b32 s2, 0
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288 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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289 ; CI-NEXT: s_waitcnt lgkmcnt(0)
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290 ; CI-NEXT: s_mov_b64 s[0:1], s[6:7]
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291 ; CI-NEXT: v_mov_b32_e32 v1, 0
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292 ; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64
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293 ; CI-NEXT: s_mov_b32 s0, 0xffff
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221
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294 ; CI-NEXT: s_lshr_b32 s1, s8, 16
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150
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295 ; CI-NEXT: s_mov_b64 s[6:7], s[2:3]
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296 ; CI-NEXT: s_waitcnt vmcnt(0)
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297 ; CI-NEXT: v_and_b32_e32 v3, s0, v2
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298 ; CI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
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221
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299 ; CI-NEXT: v_lshl_b32_e32 v2, s1, v2
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150
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300 ; CI-NEXT: v_lshl_b32_e32 v3, s8, v3
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301 ; CI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
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302 ; CI-NEXT: v_and_b32_e32 v3, s0, v3
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303 ; CI-NEXT: v_or_b32_e32 v2, v3, v2
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304 ; CI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
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305 ; CI-NEXT: s_endpgm
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221
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306 ;
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307 ; GFX10-LABEL: shl_s_v_v2i16:
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308 ; GFX10: ; %bb.0:
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309 ; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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310 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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311 ; GFX10-NEXT: s_load_dword s0, s[0:1], 0x34
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312 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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313 ; GFX10-NEXT: global_load_dword v1, v0, s[6:7]
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314 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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315 ; GFX10-NEXT: v_pk_lshlrev_b16 v1, v1, s0
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316 ; GFX10-NEXT: global_store_dword v0, v1, s[4:5]
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317 ; GFX10-NEXT: s_endpgm
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150
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318 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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319 %tid.ext = sext i32 %tid to i64
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320 %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
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321 %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
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322 %vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
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323 %result = shl <2 x i16> %sgpr, %vgpr
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324 store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
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325 ret void
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326 }
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327
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328 define amdgpu_kernel void @shl_imm_v_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
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329 ; GFX9-LABEL: shl_imm_v_v2i16:
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330 ; GFX9: ; %bb.0:
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331 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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221
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332 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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150
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333 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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221
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334 ; GFX9-NEXT: global_load_dword v1, v0, s[2:3]
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150
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335 ; GFX9-NEXT: s_waitcnt vmcnt(0)
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221
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336 ; GFX9-NEXT: v_pk_lshlrev_b16 v1, v1, 8 op_sel_hi:[1,0]
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337 ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
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150
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338 ; GFX9-NEXT: s_endpgm
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339 ;
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340 ; VI-LABEL: shl_imm_v_v2i16:
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341 ; VI: ; %bb.0:
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342 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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343 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
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173
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344 ; VI-NEXT: v_mov_b32_e32 v4, 8
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150
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345 ; VI-NEXT: s_waitcnt lgkmcnt(0)
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346 ; VI-NEXT: v_mov_b32_e32 v1, s3
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347 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
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348 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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221
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349 ; VI-NEXT: flat_load_dword v3, v[0:1]
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350 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
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351 ; VI-NEXT: v_mov_b32_e32 v1, s1
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352 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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353 ; VI-NEXT: s_waitcnt vmcnt(0)
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354 ; VI-NEXT: v_lshlrev_b16_e64 v2, v3, 8
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355 ; VI-NEXT: v_lshlrev_b16_sdwa v3, v3, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
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356 ; VI-NEXT: v_or_b32_e32 v2, v2, v3
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357 ; VI-NEXT: flat_store_dword v[0:1], v2
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150
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358 ; VI-NEXT: s_endpgm
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359 ;
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360 ; CI-LABEL: shl_imm_v_v2i16:
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361 ; CI: ; %bb.0:
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173
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362 ; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
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363 ; CI-NEXT: s_mov_b32 s3, 0xf000
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364 ; CI-NEXT: s_mov_b32 s2, 0
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150
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365 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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366 ; CI-NEXT: v_mov_b32_e32 v1, 0
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367 ; CI-NEXT: s_waitcnt lgkmcnt(0)
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173
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368 ; CI-NEXT: s_mov_b64 s[0:1], s[6:7]
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369 ; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64
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370 ; CI-NEXT: s_mov_b64 s[6:7], s[2:3]
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150
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371 ; CI-NEXT: s_waitcnt vmcnt(0)
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372 ; CI-NEXT: v_and_b32_e32 v3, 0xffff, v2
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373 ; CI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
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374 ; CI-NEXT: v_lshl_b32_e32 v2, 8, v2
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375 ; CI-NEXT: v_lshl_b32_e32 v3, 8, v3
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376 ; CI-NEXT: v_lshlrev_b32_e32 v2, 16, v2
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377 ; CI-NEXT: v_and_b32_e32 v3, 0xfff8, v3
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378 ; CI-NEXT: v_or_b32_e32 v2, v3, v2
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173
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379 ; CI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
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150
|
380 ; CI-NEXT: s_endpgm
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221
|
381 ;
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382 ; GFX10-LABEL: shl_imm_v_v2i16:
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383 ; GFX10: ; %bb.0:
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384 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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385 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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386 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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387 ; GFX10-NEXT: global_load_dword v1, v0, s[2:3]
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388 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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389 ; GFX10-NEXT: v_pk_lshlrev_b16 v1, v1, 8 op_sel_hi:[1,0]
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390 ; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
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391 ; GFX10-NEXT: s_endpgm
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150
|
392 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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393 %tid.ext = sext i32 %tid to i64
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394 %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
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395 %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
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396 %vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
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397 %result = shl <2 x i16> <i16 8, i16 8>, %vgpr
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398 store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
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399 ret void
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400 }
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401
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402 define amdgpu_kernel void @shl_v_imm_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in) #0 {
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403 ; GFX9-LABEL: shl_v_imm_v2i16:
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404 ; GFX9: ; %bb.0:
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405 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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221
|
406 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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150
|
407 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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221
|
408 ; GFX9-NEXT: global_load_dword v1, v0, s[2:3]
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150
|
409 ; GFX9-NEXT: s_waitcnt vmcnt(0)
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221
|
410 ; GFX9-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
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411 ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
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|
150
|
412 ; GFX9-NEXT: s_endpgm
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413 ;
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414 ; VI-LABEL: shl_v_imm_v2i16:
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415 ; VI: ; %bb.0:
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416 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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417 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
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418 ; VI-NEXT: s_waitcnt lgkmcnt(0)
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419 ; VI-NEXT: v_mov_b32_e32 v1, s3
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420 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
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421 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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221
|
422 ; VI-NEXT: flat_load_dword v3, v[0:1]
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423 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
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424 ; VI-NEXT: v_mov_b32_e32 v1, s1
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425 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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426 ; VI-NEXT: s_waitcnt vmcnt(0)
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427 ; VI-NEXT: v_lshlrev_b32_e32 v2, 8, v3
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428 ; VI-NEXT: v_and_b32_e32 v2, 0xff000000, v2
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429 ; VI-NEXT: v_lshlrev_b16_e32 v3, 8, v3
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430 ; VI-NEXT: v_or_b32_e32 v2, v3, v2
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431 ; VI-NEXT: flat_store_dword v[0:1], v2
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150
|
432 ; VI-NEXT: s_endpgm
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433 ;
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434 ; CI-LABEL: shl_v_imm_v2i16:
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435 ; CI: ; %bb.0:
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173
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436 ; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
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437 ; CI-NEXT: s_mov_b32 s3, 0xf000
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438 ; CI-NEXT: s_mov_b32 s2, 0
|
|
150
|
439 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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|
|
440 ; CI-NEXT: v_mov_b32_e32 v1, 0
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|
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441 ; CI-NEXT: s_waitcnt lgkmcnt(0)
|
|
173
|
442 ; CI-NEXT: s_mov_b64 s[0:1], s[6:7]
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443 ; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64
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444 ; CI-NEXT: s_mov_b64 s[6:7], s[2:3]
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150
|
445 ; CI-NEXT: s_waitcnt vmcnt(0)
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|
446 ; CI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
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|
|
447 ; CI-NEXT: v_and_b32_e32 v2, 0xff00ff00, v2
|
|
173
|
448 ; CI-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
|
|
150
|
449 ; CI-NEXT: s_endpgm
|
|
221
|
450 ;
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|
|
451 ; GFX10-LABEL: shl_v_imm_v2i16:
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|
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452 ; GFX10: ; %bb.0:
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|
453 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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|
454 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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|
455 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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|
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456 ; GFX10-NEXT: global_load_dword v1, v0, s[2:3]
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|
|
457 ; GFX10-NEXT: s_waitcnt vmcnt(0)
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458 ; GFX10-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
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|
|
459 ; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
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|
|
460 ; GFX10-NEXT: s_endpgm
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|
150
|
461 %tid = call i32 @llvm.amdgcn.workitem.id.x()
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462 %tid.ext = sext i32 %tid to i64
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463 %in.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in, i64 %tid.ext
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464 %out.gep = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 %tid.ext
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465 %vgpr = load <2 x i16>, <2 x i16> addrspace(1)* %in.gep
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466 %result = shl <2 x i16> %vgpr, <i16 8, i16 8>
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|
467 store <2 x i16> %result, <2 x i16> addrspace(1)* %out.gep
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|
468 ret void
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|
|
469 }
|
|
|
470
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|
|
471 define amdgpu_kernel void @v_shl_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) #0 {
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|
472 ; GFX9-LABEL: v_shl_v4i16:
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|
|
473 ; GFX9: ; %bb.0:
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|
|
474 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
|
221
|
475 ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 3, v0
|
|
150
|
476 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
221
|
477 ; GFX9-NEXT: global_load_dwordx2 v[0:1], v4, s[2:3]
|
|
|
478 ; GFX9-NEXT: global_load_dwordx2 v[2:3], v4, s[2:3] offset:8
|
|
150
|
479 ; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
221
|
480 ; GFX9-NEXT: v_pk_lshlrev_b16 v1, v3, v1
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|
|
481 ; GFX9-NEXT: v_pk_lshlrev_b16 v0, v2, v0
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|
|
482 ; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
|
|
150
|
483 ; GFX9-NEXT: s_endpgm
|
|
|
484 ;
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|
|
485 ; VI-LABEL: v_shl_v4i16:
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|
|
486 ; VI: ; %bb.0:
|
|
|
487 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
|
221
|
488 ; VI-NEXT: v_lshlrev_b32_e32 v4, 3, v0
|
|
150
|
489 ; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
490 ; VI-NEXT: v_mov_b32_e32 v1, s3
|
|
221
|
491 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4
|
|
150
|
492 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
221
|
493 ; VI-NEXT: v_add_u32_e32 v2, vcc, 8, v0
|
|
|
494 ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
|
|
150
|
495 ; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
|
|
221
|
496 ; VI-NEXT: flat_load_dwordx2 v[2:3], v[2:3]
|
|
|
497 ; VI-NEXT: v_mov_b32_e32 v5, s1
|
|
|
498 ; VI-NEXT: v_add_u32_e32 v4, vcc, s0, v4
|
|
|
499 ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
|
|
|
500 ; VI-NEXT: s_waitcnt vmcnt(0)
|
|
|
501 ; VI-NEXT: v_lshlrev_b16_e32 v6, v3, v1
|
|
|
502 ; VI-NEXT: v_lshlrev_b16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
|
|
503 ; VI-NEXT: v_lshlrev_b16_e32 v3, v2, v0
|
|
|
504 ; VI-NEXT: v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
|
150
|
505 ; VI-NEXT: v_or_b32_e32 v1, v6, v1
|
|
221
|
506 ; VI-NEXT: v_or_b32_e32 v0, v3, v0
|
|
|
507 ; VI-NEXT: flat_store_dwordx2 v[4:5], v[0:1]
|
|
150
|
508 ; VI-NEXT: s_endpgm
|
|
|
509 ;
|
|
|
510 ; CI-LABEL: v_shl_v4i16:
|
|
|
511 ; CI: ; %bb.0:
|
|
173
|
512 ; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
|
|
|
513 ; CI-NEXT: s_mov_b32 s3, 0xf000
|
|
|
514 ; CI-NEXT: s_mov_b32 s2, 0
|
|
150
|
515 ; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
|
|
516 ; CI-NEXT: v_mov_b32_e32 v1, 0
|
|
|
517 ; CI-NEXT: s_waitcnt lgkmcnt(0)
|
|
173
|
518 ; CI-NEXT: s_mov_b64 s[0:1], s[6:7]
|
|
|
519 ; CI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
|
|
|
520 ; CI-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[0:3], 0 addr64 offset:8
|
|
221
|
521 ; CI-NEXT: s_mov_b32 s0, 0xffff
|
|
173
|
522 ; CI-NEXT: s_mov_b64 s[6:7], s[2:3]
|
|
150
|
523 ; CI-NEXT: s_waitcnt vmcnt(1)
|
|
|
524 ; CI-NEXT: v_lshrrev_b32_e32 v6, 16, v2
|
|
|
525 ; CI-NEXT: s_waitcnt vmcnt(0)
|
|
221
|
526 ; CI-NEXT: v_and_b32_e32 v8, s0, v4
|
|
150
|
527 ; CI-NEXT: v_lshrrev_b32_e32 v4, 16, v4
|
|
221
|
528 ; CI-NEXT: v_and_b32_e32 v9, s0, v5
|
|
150
|
529 ; CI-NEXT: v_lshrrev_b32_e32 v7, 16, v3
|
|
|
530 ; CI-NEXT: v_lshrrev_b32_e32 v5, 16, v5
|
|
|
531 ; CI-NEXT: v_lshl_b32_e32 v5, v7, v5
|
|
|
532 ; CI-NEXT: v_lshl_b32_e32 v3, v3, v9
|
|
|
533 ; CI-NEXT: v_lshl_b32_e32 v4, v6, v4
|
|
|
534 ; CI-NEXT: v_lshl_b32_e32 v2, v2, v8
|
|
|
535 ; CI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
|
|
221
|
536 ; CI-NEXT: v_and_b32_e32 v3, s0, v3
|
|
150
|
537 ; CI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
221
|
538 ; CI-NEXT: v_and_b32_e32 v2, s0, v2
|
|
150
|
539 ; CI-NEXT: v_or_b32_e32 v3, v3, v5
|
|
|
540 ; CI-NEXT: v_or_b32_e32 v2, v2, v4
|
|
173
|
541 ; CI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
|
|
150
|
542 ; CI-NEXT: s_endpgm
|
|
221
|
543 ;
|
|
|
544 ; GFX10-LABEL: v_shl_v4i16:
|
|
|
545 ; GFX10: ; %bb.0:
|
|
|
546 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
|
|
547 ; GFX10-NEXT: v_lshlrev_b32_e32 v4, 3, v0
|
|
|
548 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
549 ; GFX10-NEXT: s_clause 0x1
|
|
|
550 ; GFX10-NEXT: global_load_dwordx2 v[0:1], v4, s[2:3]
|
|
|
551 ; GFX10-NEXT: global_load_dwordx2 v[2:3], v4, s[2:3] offset:8
|
|
|
552 ; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
|
553 ; GFX10-NEXT: v_pk_lshlrev_b16 v1, v3, v1
|
|
|
554 ; GFX10-NEXT: v_pk_lshlrev_b16 v0, v2, v0
|
|
|
555 ; GFX10-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
|
|
|
556 ; GFX10-NEXT: s_endpgm
|
|
150
|
557 %tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
|
558 %tid.ext = sext i32 %tid to i64
|
|
|
559 %in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext
|
|
|
560 %out.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %out, i64 %tid.ext
|
|
|
561 %b_ptr = getelementptr <4 x i16>, <4 x i16> addrspace(1)* %in.gep, i32 1
|
|
|
562 %a = load <4 x i16>, <4 x i16> addrspace(1)* %in.gep
|
|
|
563 %b = load <4 x i16>, <4 x i16> addrspace(1)* %b_ptr
|
|
|
564 %result = shl <4 x i16> %a, %b
|
|
|
565 store <4 x i16> %result, <4 x i16> addrspace(1)* %out.gep
|
|
|
566 ret void
|
|
|
567 }
|
|
|
568
|
|
|
569 define amdgpu_kernel void @shl_v_imm_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in) #0 {
|
|
|
570 ; GFX9-LABEL: shl_v_imm_v4i16:
|
|
|
571 ; GFX9: ; %bb.0:
|
|
|
572 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
|
|
573 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 3, v0
|
|
|
574 ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
221
|
575 ; GFX9-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3]
|
|
150
|
576 ; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
|
577 ; GFX9-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
|
|
|
578 ; GFX9-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
|
|
221
|
579 ; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
|
|
150
|
580 ; GFX9-NEXT: s_endpgm
|
|
|
581 ;
|
|
|
582 ; VI-LABEL: shl_v_imm_v4i16:
|
|
|
583 ; VI: ; %bb.0:
|
|
|
584 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
|
|
585 ; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v0
|
|
|
586 ; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
221
|
587 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
|
|
150
|
588 ; VI-NEXT: v_mov_b32_e32 v1, s3
|
|
|
589 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
|
590 ; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
|
|
221
|
591 ; VI-NEXT: s_mov_b32 s2, 0xff000000
|
|
150
|
592 ; VI-NEXT: v_mov_b32_e32 v3, s1
|
|
221
|
593 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
|
|
150
|
594 ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
221
|
595 ; VI-NEXT: s_waitcnt vmcnt(0)
|
|
150
|
596 ; VI-NEXT: v_lshlrev_b32_e32 v4, 8, v1
|
|
|
597 ; VI-NEXT: v_lshlrev_b16_e32 v5, 8, v0
|
|
|
598 ; VI-NEXT: v_lshlrev_b32_e32 v0, 8, v0
|
|
221
|
599 ; VI-NEXT: v_and_b32_e32 v0, s2, v0
|
|
150
|
600 ; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v1
|
|
221
|
601 ; VI-NEXT: v_and_b32_e32 v4, s2, v4
|
|
150
|
602 ; VI-NEXT: v_or_b32_e32 v1, v1, v4
|
|
|
603 ; VI-NEXT: v_or_b32_e32 v0, v5, v0
|
|
|
604 ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
|
|
|
605 ; VI-NEXT: s_endpgm
|
|
|
606 ;
|
|
|
607 ; CI-LABEL: shl_v_imm_v4i16:
|
|
|
608 ; CI: ; %bb.0:
|
|
173
|
609 ; CI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
|
|
|
610 ; CI-NEXT: s_mov_b32 s3, 0xf000
|
|
|
611 ; CI-NEXT: s_mov_b32 s2, 0
|
|
150
|
612 ; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
|
|
|
613 ; CI-NEXT: v_mov_b32_e32 v1, 0
|
|
|
614 ; CI-NEXT: s_waitcnt lgkmcnt(0)
|
|
173
|
615 ; CI-NEXT: s_mov_b64 s[0:1], s[6:7]
|
|
|
616 ; CI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64
|
|
221
|
617 ; CI-NEXT: s_mov_b32 s0, 0xff00
|
|
173
|
618 ; CI-NEXT: s_mov_b64 s[6:7], s[2:3]
|
|
150
|
619 ; CI-NEXT: s_waitcnt vmcnt(0)
|
|
|
620 ; CI-NEXT: v_lshrrev_b32_e32 v4, 8, v3
|
|
|
621 ; CI-NEXT: v_lshlrev_b32_e32 v3, 8, v3
|
|
221
|
622 ; CI-NEXT: v_and_b32_e32 v4, s0, v4
|
|
150
|
623 ; CI-NEXT: v_lshlrev_b32_e32 v2, 8, v2
|
|
221
|
624 ; CI-NEXT: v_and_b32_e32 v3, s0, v3
|
|
150
|
625 ; CI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
|
|
|
626 ; CI-NEXT: v_or_b32_e32 v3, v3, v4
|
|
|
627 ; CI-NEXT: v_and_b32_e32 v2, 0xff00ff00, v2
|
|
173
|
628 ; CI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64
|
|
150
|
629 ; CI-NEXT: s_endpgm
|
|
221
|
630 ;
|
|
|
631 ; GFX10-LABEL: shl_v_imm_v4i16:
|
|
|
632 ; GFX10: ; %bb.0:
|
|
|
633 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
|
|
634 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 3, v0
|
|
|
635 ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
|
636 ; GFX10-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3]
|
|
|
637 ; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
|
638 ; GFX10-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
|
|
|
639 ; GFX10-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
|
|
|
640 ; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
|
|
|
641 ; GFX10-NEXT: s_endpgm
|
|
150
|
642 %tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
|
643 %tid.ext = sext i32 %tid to i64
|
|
|
644 %in.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %in, i64 %tid.ext
|
|
|
645 %out.gep = getelementptr inbounds <4 x i16>, <4 x i16> addrspace(1)* %out, i64 %tid.ext
|
|
|
646 %vgpr = load <4 x i16>, <4 x i16> addrspace(1)* %in.gep
|
|
|
647 %result = shl <4 x i16> %vgpr, <i16 8, i16 8, i16 8, i16 8>
|
|
|
648 store <4 x i16> %result, <4 x i16> addrspace(1)* %out.gep
|
|
|
649 ret void
|
|
|
650 }
|
|
|
651
|
|
|
652 declare i32 @llvm.amdgcn.workitem.id.x() #1
|
|
|
653
|
|
|
654 attributes #0 = { nounwind }
|
|
|
655 attributes #1 = { nounwind readnone }
|
