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83
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1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s -o -| FileCheck %s
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2
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3 define <8 x i16> @smull_v8i8_v8i16(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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4 ; CHECK-LABEL: smull_v8i8_v8i16:
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5 ; CHECK: smull {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
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95
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6 %tmp1 = load <8 x i8>, <8 x i8>* %A
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7 %tmp2 = load <8 x i8>, <8 x i8>* %B
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83
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8 %tmp3 = sext <8 x i8> %tmp1 to <8 x i16>
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9 %tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
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10 %tmp5 = mul <8 x i16> %tmp3, %tmp4
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11 ret <8 x i16> %tmp5
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12 }
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13
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14 define <4 x i32> @smull_v4i16_v4i32(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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15 ; CHECK-LABEL: smull_v4i16_v4i32:
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16 ; CHECK: smull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
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95
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17 %tmp1 = load <4 x i16>, <4 x i16>* %A
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18 %tmp2 = load <4 x i16>, <4 x i16>* %B
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83
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19 %tmp3 = sext <4 x i16> %tmp1 to <4 x i32>
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20 %tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
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21 %tmp5 = mul <4 x i32> %tmp3, %tmp4
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22 ret <4 x i32> %tmp5
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23 }
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24
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25 define <2 x i64> @smull_v2i32_v2i64(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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26 ; CHECK-LABEL: smull_v2i32_v2i64:
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27 ; CHECK: smull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
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95
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28 %tmp1 = load <2 x i32>, <2 x i32>* %A
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29 %tmp2 = load <2 x i32>, <2 x i32>* %B
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83
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30 %tmp3 = sext <2 x i32> %tmp1 to <2 x i64>
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31 %tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
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32 %tmp5 = mul <2 x i64> %tmp3, %tmp4
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33 ret <2 x i64> %tmp5
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34 }
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35
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36 define <8 x i16> @umull_v8i8_v8i16(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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37 ; CHECK-LABEL: umull_v8i8_v8i16:
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38 ; CHECK: umull {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
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95
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39 %tmp1 = load <8 x i8>, <8 x i8>* %A
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40 %tmp2 = load <8 x i8>, <8 x i8>* %B
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83
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41 %tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
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42 %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
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43 %tmp5 = mul <8 x i16> %tmp3, %tmp4
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44 ret <8 x i16> %tmp5
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45 }
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46
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47 define <4 x i32> @umull_v4i16_v4i32(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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48 ; CHECK-LABEL: umull_v4i16_v4i32:
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49 ; CHECK: umull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
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95
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50 %tmp1 = load <4 x i16>, <4 x i16>* %A
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51 %tmp2 = load <4 x i16>, <4 x i16>* %B
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83
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52 %tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
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53 %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
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54 %tmp5 = mul <4 x i32> %tmp3, %tmp4
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55 ret <4 x i32> %tmp5
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56 }
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57
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58 define <2 x i64> @umull_v2i32_v2i64(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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59 ; CHECK-LABEL: umull_v2i32_v2i64:
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60 ; CHECK: umull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
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95
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61 %tmp1 = load <2 x i32>, <2 x i32>* %A
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62 %tmp2 = load <2 x i32>, <2 x i32>* %B
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83
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63 %tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
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64 %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
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65 %tmp5 = mul <2 x i64> %tmp3, %tmp4
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66 ret <2 x i64> %tmp5
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67 }
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68
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69 define <8 x i16> @smlal_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
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70 ; CHECK-LABEL: smlal_v8i8_v8i16:
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71 ; CHECK: smlal {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
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95
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72 %tmp1 = load <8 x i16>, <8 x i16>* %A
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73 %tmp2 = load <8 x i8>, <8 x i8>* %B
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74 %tmp3 = load <8 x i8>, <8 x i8>* %C
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83
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75 %tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
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76 %tmp5 = sext <8 x i8> %tmp3 to <8 x i16>
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77 %tmp6 = mul <8 x i16> %tmp4, %tmp5
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78 %tmp7 = add <8 x i16> %tmp1, %tmp6
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79 ret <8 x i16> %tmp7
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80 }
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81
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82 define <4 x i32> @smlal_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
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83 ; CHECK-LABEL: smlal_v4i16_v4i32:
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84 ; CHECK: smlal {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
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95
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85 %tmp1 = load <4 x i32>, <4 x i32>* %A
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86 %tmp2 = load <4 x i16>, <4 x i16>* %B
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87 %tmp3 = load <4 x i16>, <4 x i16>* %C
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83
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88 %tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
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89 %tmp5 = sext <4 x i16> %tmp3 to <4 x i32>
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90 %tmp6 = mul <4 x i32> %tmp4, %tmp5
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91 %tmp7 = add <4 x i32> %tmp1, %tmp6
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92 ret <4 x i32> %tmp7
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93 }
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94
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95 define <2 x i64> @smlal_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
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96 ; CHECK-LABEL: smlal_v2i32_v2i64:
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97 ; CHECK: smlal {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
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95
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98 %tmp1 = load <2 x i64>, <2 x i64>* %A
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99 %tmp2 = load <2 x i32>, <2 x i32>* %B
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100 %tmp3 = load <2 x i32>, <2 x i32>* %C
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83
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101 %tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
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102 %tmp5 = sext <2 x i32> %tmp3 to <2 x i64>
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103 %tmp6 = mul <2 x i64> %tmp4, %tmp5
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104 %tmp7 = add <2 x i64> %tmp1, %tmp6
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105 ret <2 x i64> %tmp7
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106 }
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107
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108 define <8 x i16> @umlal_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
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109 ; CHECK-LABEL: umlal_v8i8_v8i16:
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110 ; CHECK: umlal {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
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95
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111 %tmp1 = load <8 x i16>, <8 x i16>* %A
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112 %tmp2 = load <8 x i8>, <8 x i8>* %B
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113 %tmp3 = load <8 x i8>, <8 x i8>* %C
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83
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114 %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
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115 %tmp5 = zext <8 x i8> %tmp3 to <8 x i16>
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116 %tmp6 = mul <8 x i16> %tmp4, %tmp5
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117 %tmp7 = add <8 x i16> %tmp1, %tmp6
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118 ret <8 x i16> %tmp7
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119 }
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120
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121 define <4 x i32> @umlal_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
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122 ; CHECK-LABEL: umlal_v4i16_v4i32:
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123 ; CHECK: umlal {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
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95
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124 %tmp1 = load <4 x i32>, <4 x i32>* %A
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125 %tmp2 = load <4 x i16>, <4 x i16>* %B
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126 %tmp3 = load <4 x i16>, <4 x i16>* %C
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83
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127 %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
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128 %tmp5 = zext <4 x i16> %tmp3 to <4 x i32>
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129 %tmp6 = mul <4 x i32> %tmp4, %tmp5
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130 %tmp7 = add <4 x i32> %tmp1, %tmp6
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131 ret <4 x i32> %tmp7
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132 }
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133
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134 define <2 x i64> @umlal_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
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135 ; CHECK-LABEL: umlal_v2i32_v2i64:
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136 ; CHECK: umlal {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
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95
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137 %tmp1 = load <2 x i64>, <2 x i64>* %A
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138 %tmp2 = load <2 x i32>, <2 x i32>* %B
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139 %tmp3 = load <2 x i32>, <2 x i32>* %C
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83
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140 %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
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141 %tmp5 = zext <2 x i32> %tmp3 to <2 x i64>
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142 %tmp6 = mul <2 x i64> %tmp4, %tmp5
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143 %tmp7 = add <2 x i64> %tmp1, %tmp6
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144 ret <2 x i64> %tmp7
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145 }
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146
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147 define <8 x i16> @smlsl_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
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148 ; CHECK-LABEL: smlsl_v8i8_v8i16:
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149 ; CHECK: smlsl {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
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95
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150 %tmp1 = load <8 x i16>, <8 x i16>* %A
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151 %tmp2 = load <8 x i8>, <8 x i8>* %B
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152 %tmp3 = load <8 x i8>, <8 x i8>* %C
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83
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153 %tmp4 = sext <8 x i8> %tmp2 to <8 x i16>
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154 %tmp5 = sext <8 x i8> %tmp3 to <8 x i16>
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155 %tmp6 = mul <8 x i16> %tmp4, %tmp5
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156 %tmp7 = sub <8 x i16> %tmp1, %tmp6
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157 ret <8 x i16> %tmp7
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158 }
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159
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160 define <4 x i32> @smlsl_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
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161 ; CHECK-LABEL: smlsl_v4i16_v4i32:
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162 ; CHECK: smlsl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
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95
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163 %tmp1 = load <4 x i32>, <4 x i32>* %A
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164 %tmp2 = load <4 x i16>, <4 x i16>* %B
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165 %tmp3 = load <4 x i16>, <4 x i16>* %C
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83
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166 %tmp4 = sext <4 x i16> %tmp2 to <4 x i32>
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167 %tmp5 = sext <4 x i16> %tmp3 to <4 x i32>
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168 %tmp6 = mul <4 x i32> %tmp4, %tmp5
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169 %tmp7 = sub <4 x i32> %tmp1, %tmp6
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170 ret <4 x i32> %tmp7
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171 }
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172
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173 define <2 x i64> @smlsl_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
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174 ; CHECK-LABEL: smlsl_v2i32_v2i64:
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175 ; CHECK: smlsl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
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95
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176 %tmp1 = load <2 x i64>, <2 x i64>* %A
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177 %tmp2 = load <2 x i32>, <2 x i32>* %B
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178 %tmp3 = load <2 x i32>, <2 x i32>* %C
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83
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179 %tmp4 = sext <2 x i32> %tmp2 to <2 x i64>
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180 %tmp5 = sext <2 x i32> %tmp3 to <2 x i64>
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181 %tmp6 = mul <2 x i64> %tmp4, %tmp5
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182 %tmp7 = sub <2 x i64> %tmp1, %tmp6
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183 ret <2 x i64> %tmp7
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184 }
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185
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186 define <8 x i16> @umlsl_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
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187 ; CHECK-LABEL: umlsl_v8i8_v8i16:
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188 ; CHECK: umlsl {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
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95
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189 %tmp1 = load <8 x i16>, <8 x i16>* %A
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190 %tmp2 = load <8 x i8>, <8 x i8>* %B
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191 %tmp3 = load <8 x i8>, <8 x i8>* %C
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83
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192 %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
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193 %tmp5 = zext <8 x i8> %tmp3 to <8 x i16>
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194 %tmp6 = mul <8 x i16> %tmp4, %tmp5
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195 %tmp7 = sub <8 x i16> %tmp1, %tmp6
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196 ret <8 x i16> %tmp7
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197 }
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198
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199 define <4 x i32> @umlsl_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
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200 ; CHECK-LABEL: umlsl_v4i16_v4i32:
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201 ; CHECK: umlsl {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
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95
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202 %tmp1 = load <4 x i32>, <4 x i32>* %A
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203 %tmp2 = load <4 x i16>, <4 x i16>* %B
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204 %tmp3 = load <4 x i16>, <4 x i16>* %C
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83
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205 %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
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206 %tmp5 = zext <4 x i16> %tmp3 to <4 x i32>
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207 %tmp6 = mul <4 x i32> %tmp4, %tmp5
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208 %tmp7 = sub <4 x i32> %tmp1, %tmp6
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209 ret <4 x i32> %tmp7
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210 }
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211
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212 define <2 x i64> @umlsl_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
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213 ; CHECK-LABEL: umlsl_v2i32_v2i64:
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214 ; CHECK: umlsl {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
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95
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215 %tmp1 = load <2 x i64>, <2 x i64>* %A
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216 %tmp2 = load <2 x i32>, <2 x i32>* %B
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217 %tmp3 = load <2 x i32>, <2 x i32>* %C
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83
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218 %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
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219 %tmp5 = zext <2 x i32> %tmp3 to <2 x i64>
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220 %tmp6 = mul <2 x i64> %tmp4, %tmp5
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221 %tmp7 = sub <2 x i64> %tmp1, %tmp6
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222 ret <2 x i64> %tmp7
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223 }
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224
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225 ; SMULL recognizing BUILD_VECTORs with sign/zero-extended elements.
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226 define <8 x i16> @smull_extvec_v8i8_v8i16(<8 x i8> %arg) nounwind {
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227 ; CHECK-LABEL: smull_extvec_v8i8_v8i16:
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228 ; CHECK: smull {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
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229 %tmp3 = sext <8 x i8> %arg to <8 x i16>
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230 %tmp4 = mul <8 x i16> %tmp3, <i16 -12, i16 -12, i16 -12, i16 -12, i16 -12, i16 -12, i16 -12, i16 -12>
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231 ret <8 x i16> %tmp4
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232 }
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233
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234 define <8 x i16> @smull_noextvec_v8i8_v8i16(<8 x i8> %arg) nounwind {
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235 ; Do not use SMULL if the BUILD_VECTOR element values are too big.
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236 ; CHECK-LABEL: smull_noextvec_v8i8_v8i16:
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237 ; CHECK: movz
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238 ; CHECK: mul {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
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239 %tmp3 = sext <8 x i8> %arg to <8 x i16>
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240 %tmp4 = mul <8 x i16> %tmp3, <i16 -999, i16 -999, i16 -999, i16 -999, i16 -999, i16 -999, i16 -999, i16 -999>
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241 ret <8 x i16> %tmp4
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242 }
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243
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244 define <4 x i32> @smull_extvec_v4i16_v4i32(<4 x i16> %arg) nounwind {
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245 ; CHECK-LABEL: smull_extvec_v4i16_v4i32:
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246 ; CHECK: smull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
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247 %tmp3 = sext <4 x i16> %arg to <4 x i32>
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248 %tmp4 = mul <4 x i32> %tmp3, <i32 -12, i32 -12, i32 -12, i32 -12>
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249 ret <4 x i32> %tmp4
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250 }
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251
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252 define <2 x i64> @smull_extvec_v2i32_v2i64(<2 x i32> %arg) nounwind {
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253 ; CHECK: smull_extvec_v2i32_v2i64
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254 ; CHECK: smull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
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255 %tmp3 = sext <2 x i32> %arg to <2 x i64>
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256 %tmp4 = mul <2 x i64> %tmp3, <i64 -1234, i64 -1234>
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257 ret <2 x i64> %tmp4
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258 }
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259
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260 define <8 x i16> @umull_extvec_v8i8_v8i16(<8 x i8> %arg) nounwind {
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261 ; CHECK-LABEL: umull_extvec_v8i8_v8i16:
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262 ; CHECK: umull {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
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263 %tmp3 = zext <8 x i8> %arg to <8 x i16>
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264 %tmp4 = mul <8 x i16> %tmp3, <i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12>
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265 ret <8 x i16> %tmp4
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266 }
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267
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268 define <8 x i16> @umull_noextvec_v8i8_v8i16(<8 x i8> %arg) nounwind {
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269 ; Do not use SMULL if the BUILD_VECTOR element values are too big.
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270 ; CHECK-LABEL: umull_noextvec_v8i8_v8i16:
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271 ; CHECK: movz
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272 ; CHECK: mul {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
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273 %tmp3 = zext <8 x i8> %arg to <8 x i16>
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274 %tmp4 = mul <8 x i16> %tmp3, <i16 999, i16 999, i16 999, i16 999, i16 999, i16 999, i16 999, i16 999>
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275 ret <8 x i16> %tmp4
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276 }
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277
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278 define <4 x i32> @umull_extvec_v4i16_v4i32(<4 x i16> %arg) nounwind {
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279 ; CHECK-LABEL: umull_extvec_v4i16_v4i32:
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280 ; CHECK: umull {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
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281 %tmp3 = zext <4 x i16> %arg to <4 x i32>
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282 %tmp4 = mul <4 x i32> %tmp3, <i32 1234, i32 1234, i32 1234, i32 1234>
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283 ret <4 x i32> %tmp4
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284 }
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285
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286 define <2 x i64> @umull_extvec_v2i32_v2i64(<2 x i32> %arg) nounwind {
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287 ; CHECK-LABEL: umull_extvec_v2i32_v2i64:
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288 ; CHECK: umull {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
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289 %tmp3 = zext <2 x i32> %arg to <2 x i64>
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290 %tmp4 = mul <2 x i64> %tmp3, <i64 1234, i64 1234>
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291 ret <2 x i64> %tmp4
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292 }
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293
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294 define i16 @smullWithInconsistentExtensions(<8 x i8> %vec) {
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295 ; If one operand has a zero-extend and the other a sign-extend, smull
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296 ; cannot be used.
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297 ; CHECK-LABEL: smullWithInconsistentExtensions:
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298 ; CHECK: mul {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
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299 %1 = sext <8 x i8> %vec to <8 x i16>
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300 %2 = mul <8 x i16> %1, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
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301 %3 = extractelement <8 x i16> %2, i32 0
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302 ret i16 %3
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303 }
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304
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305 define void @distribute(i16* %dst, i8* %src, i32 %mul) nounwind {
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306 entry:
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307 ; CHECK-LABEL: distribute:
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308 ; CHECK: umull [[REG1:(v[0-9]+.8h)]], {{v[0-9]+}}.8b, [[REG2:(v[0-9]+.8b)]]
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309 ; CHECK: umlal [[REG1]], {{v[0-9]+}}.8b, [[REG2]]
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310 %0 = trunc i32 %mul to i8
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311 %1 = insertelement <8 x i8> undef, i8 %0, i32 0
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312 %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer
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313 %3 = tail call <16 x i8> @llvm.aarch64.neon.vld1.v16i8(i8* %src, i32 1)
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314 %4 = bitcast <16 x i8> %3 to <2 x double>
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315 %5 = extractelement <2 x double> %4, i32 1
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316 %6 = bitcast double %5 to <8 x i8>
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317 %7 = zext <8 x i8> %6 to <8 x i16>
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318 %8 = zext <8 x i8> %2 to <8 x i16>
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319 %9 = extractelement <2 x double> %4, i32 0
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320 %10 = bitcast double %9 to <8 x i8>
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321 %11 = zext <8 x i8> %10 to <8 x i16>
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322 %12 = add <8 x i16> %7, %11
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323 %13 = mul <8 x i16> %12, %8
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324 %14 = bitcast i16* %dst to i8*
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325 tail call void @llvm.aarch64.neon.vst1.v8i16(i8* %14, <8 x i16> %13, i32 2)
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326 ret void
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327 }
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328
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329 declare <16 x i8> @llvm.aarch64.neon.vld1.v16i8(i8*, i32) nounwind readonly
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330
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331 declare void @llvm.aarch64.neon.vst1.v8i16(i8*, <8 x i16>, i32) nounwind
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332
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