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annotate test/CodeGen/AArch64/arm64-big-endian-varargs.ll @ 100:7d135dc70f03 LLVM 3.9

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children
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1 ; RUN: llc < %s | FileCheck %s
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2
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3 ; Vararg saving must save Q registers using the equivalent of STR/STP.
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4
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5 target datalayout = "E-m:e-i64:64-i128:128-n32:64-S128"
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6 target triple = "aarch64_be-arm-none-eabi"
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8 %struct.__va_list = type { i8*, i8*, i8*, i32, i32 }
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9
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10 declare void @llvm.va_start(i8*) nounwind
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11 declare void @llvm.va_end(i8*) nounwind
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12
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13 define double @callee(i32 %a, ...) {
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14 ; CHECK: stp
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15 ; CHECK: stp
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16 ; CHECK: stp
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17 ; CHECK: stp
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18 ; CHECK: stp
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19 ; CHECK: stp
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20 entry:
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21 %vl = alloca %struct.__va_list, align 8
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22 %vl1 = bitcast %struct.__va_list* %vl to i8*
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23 call void @llvm.va_start(i8* %vl1)
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24 %vr_offs_p = getelementptr inbounds %struct.__va_list, %struct.__va_list* %vl, i64 0, i32 4
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25 %vr_offs = load i32, i32* %vr_offs_p, align 4
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26 %0 = icmp sgt i32 %vr_offs, -1
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27 br i1 %0, label %vaarg.on_stack, label %vaarg.maybe_reg
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28
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29 vaarg.maybe_reg: ; preds = %entry
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30 %new_reg_offs = add i32 %vr_offs, 16
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31 store i32 %new_reg_offs, i32* %vr_offs_p, align 4
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32 %inreg = icmp slt i32 %new_reg_offs, 1
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33 br i1 %inreg, label %vaarg.in_reg, label %vaarg.on_stack
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34
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35 vaarg.in_reg: ; preds = %vaarg.maybe_reg
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36 %reg_top_p = getelementptr inbounds %struct.__va_list, %struct.__va_list* %vl, i64 0, i32 2
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37 %reg_top = load i8*, i8** %reg_top_p, align 8
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38 %1 = sext i32 %vr_offs to i64
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39 %2 = getelementptr i8, i8* %reg_top, i64 %1
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40 %3 = ptrtoint i8* %2 to i64
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41 %align_be = add i64 %3, 8
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42 %4 = inttoptr i64 %align_be to i8*
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43 br label %vaarg.end
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44
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45 vaarg.on_stack: ; preds = %vaarg.maybe_reg, %entry
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46 %stack_p = getelementptr inbounds %struct.__va_list, %struct.__va_list* %vl, i64 0, i32 0
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47 %stack = load i8*, i8** %stack_p, align 8
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48 %new_stack = getelementptr i8, i8* %stack, i64 8
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49 store i8* %new_stack, i8** %stack_p, align 8
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50 br label %vaarg.end
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51
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52 vaarg.end: ; preds = %vaarg.on_stack, %vaarg.in_reg
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53 %.sink = phi i8* [ %4, %vaarg.in_reg ], [ %stack, %vaarg.on_stack ]
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54 %5 = bitcast i8* %.sink to double*
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55 %6 = load double, double* %5, align 8
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56 call void @llvm.va_end(i8* %vl1)
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57 ret double %6
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58 }