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annotate test/CodeGen/AArch64/arm64-copy-tuple.ll @ 100:7d135dc70f03 LLVM 3.9

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents 54457678186b
children
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77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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1 ; RUN: llc -mtriple=arm64-apple-ios -o - %s | FileCheck %s
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2
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3 ; The main purpose of this test is to find out whether copyPhysReg can deal with
54457678186b LLVM 3.6
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4 ; the memmove-like situation arising in tuples, where an early copy can clobber
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5 ; the value needed by a later one if the tuples overlap.
54457678186b LLVM 3.6
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6
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7 ; We use dummy inline asm to force LLVM to generate a COPY between the registers
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8 ; we want by clobbering all the others.
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9
54457678186b LLVM 3.6
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10 define void @test_D1D2_from_D0D1(i8* %addr) #0 {
54457678186b LLVM 3.6
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11 ; CHECK-LABEL: test_D1D2_from_D0D1:
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12 ; CHECK: mov.8b v2, v1
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13 ; CHECK: mov.8b v1, v0
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14 entry:
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15 %addr_v8i8 = bitcast i8* %addr to <8 x i8>*
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16 %vec = tail call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2.v8i8.p0v8i8(<8 x i8>* %addr_v8i8)
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17 %vec0 = extractvalue { <8 x i8>, <8 x i8> } %vec, 0
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18 %vec1 = extractvalue { <8 x i8>, <8 x i8> } %vec, 1
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19 tail call void asm sideeffect "", "~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
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20 tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
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21
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22 tail call void asm sideeffect "", "~{v0},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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23 tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
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24 ret void
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25 }
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26
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27 define void @test_D0D1_from_D1D2(i8* %addr) #0 {
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28 ; CHECK-LABEL: test_D0D1_from_D1D2:
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29 ; CHECK: mov.8b v0, v1
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30 ; CHECK: mov.8b v1, v2
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31 entry:
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32 %addr_v8i8 = bitcast i8* %addr to <8 x i8>*
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33 %vec = tail call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2.v8i8.p0v8i8(<8 x i8>* %addr_v8i8)
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34 %vec0 = extractvalue { <8 x i8>, <8 x i8> } %vec, 0
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35 %vec1 = extractvalue { <8 x i8>, <8 x i8> } %vec, 1
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36 tail call void asm sideeffect "", "~{v0},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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37 tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
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38
54457678186b LLVM 3.6
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39 tail call void asm sideeffect "", "~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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40 tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
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41 ret void
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42 }
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43
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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44 define void @test_D0D1_from_D31D0(i8* %addr) #0 {
54457678186b LLVM 3.6
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45 ; CHECK-LABEL: test_D0D1_from_D31D0:
54457678186b LLVM 3.6
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46 ; CHECK: mov.8b v1, v0
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47 ; CHECK: mov.8b v0, v31
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48 entry:
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49 %addr_v8i8 = bitcast i8* %addr to <8 x i8>*
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50 %vec = tail call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2.v8i8.p0v8i8(<8 x i8>* %addr_v8i8)
54457678186b LLVM 3.6
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51 %vec0 = extractvalue { <8 x i8>, <8 x i8> } %vec, 0
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52 %vec1 = extractvalue { <8 x i8>, <8 x i8> } %vec, 1
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53 tail call void asm sideeffect "", "~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30}"()
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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54 tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
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55
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56 tail call void asm sideeffect "", "~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
54457678186b LLVM 3.6
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57 tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
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58 ret void
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59 }
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60
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61 define void @test_D31D0_from_D0D1(i8* %addr) #0 {
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62 ; CHECK-LABEL: test_D31D0_from_D0D1:
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63 ; CHECK: mov.8b v31, v0
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64 ; CHECK: mov.8b v0, v1
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65 entry:
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66 %addr_v8i8 = bitcast i8* %addr to <8 x i8>*
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67 %vec = tail call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2.v8i8.p0v8i8(<8 x i8>* %addr_v8i8)
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68 %vec0 = extractvalue { <8 x i8>, <8 x i8> } %vec, 0
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69 %vec1 = extractvalue { <8 x i8>, <8 x i8> } %vec, 1
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70 tail call void asm sideeffect "", "~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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71 tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
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72
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73 tail call void asm sideeffect "", "~{v1},~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30}"()
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74 tail call void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, i8* %addr)
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75 ret void
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76 }
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77
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78 define void @test_D2D3D4_from_D0D1D2(i8* %addr) #0 {
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79 ; CHECK-LABEL: test_D2D3D4_from_D0D1D2:
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80 ; CHECK: mov.8b v4, v2
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81 ; CHECK: mov.8b v3, v1
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82 ; CHECK: mov.8b v2, v0
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83 entry:
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84 %addr_v8i8 = bitcast i8* %addr to <8 x i8>*
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85 %vec = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3.v8i8.p0v8i8(<8 x i8>* %addr_v8i8)
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parents:
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86 %vec0 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %vec, 0
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87 %vec1 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %vec, 1
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parents:
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88 %vec2 = extractvalue { <8 x i8>, <8 x i8>, <8 x i8> } %vec, 2
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parents:
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89
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90 tail call void asm sideeffect "", "~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
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parents:
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91 tail call void @llvm.aarch64.neon.st3.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, i8* %addr)
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parents:
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92
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93 tail call void asm sideeffect "", "~{v0},~{v1},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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94 tail call void @llvm.aarch64.neon.st3.v8i8.p0i8(<8 x i8> %vec0, <8 x i8> %vec1, <8 x i8> %vec2, i8* %addr)
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95 ret void
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96 }
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97
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98 define void @test_Q0Q1Q2_from_Q1Q2Q3(i8* %addr) #0 {
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99 ; CHECK-LABEL: test_Q0Q1Q2_from_Q1Q2Q3:
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100 ; CHECK: mov.16b v0, v1
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101 ; CHECK: mov.16b v1, v2
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102 ; CHECK: mov.16b v2, v3
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103 entry:
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104 %addr_v16i8 = bitcast i8* %addr to <16 x i8>*
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105 %vec = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3.v16i8.p0v16i8(<16 x i8>* %addr_v16i8)
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106 %vec0 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %vec, 0
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107 %vec1 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %vec, 1
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108 %vec2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8> } %vec, 2
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109 tail call void asm sideeffect "", "~{v0},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
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110 tail call void @llvm.aarch64.neon.st3.v16i8.p0i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, i8* %addr)
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111
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112 tail call void asm sideeffect "", "~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
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113 tail call void @llvm.aarch64.neon.st3.v16i8.p0i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, i8* %addr)
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114 ret void
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115 }
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116
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117 define void @test_Q1Q2Q3Q4_from_Q30Q31Q0Q1(i8* %addr) #0 {
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118 ; CHECK-LABEL: test_Q1Q2Q3Q4_from_Q30Q31Q0Q1:
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119 ; CHECK: mov.16b v4, v1
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120 ; CHECK: mov.16b v3, v0
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121 ; CHECK: mov.16b v2, v31
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122 ; CHECK: mov.16b v1, v30
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123 %addr_v16i8 = bitcast i8* %addr to <16 x i8>*
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124 %vec = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4.v16i8.p0v16i8(<16 x i8>* %addr_v16i8)
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125 %vec0 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %vec, 0
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126 %vec1 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %vec, 1
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127 %vec2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %vec, 2
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128 %vec3 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %vec, 3
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129
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130 tail call void asm sideeffect "", "~{v2},~{v3},~{v4},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29}"()
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131 tail call void @llvm.aarch64.neon.st4.v16i8.p0i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3, i8* %addr)
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132
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133 tail call void asm sideeffect "", "~{v0},~{v5},~{v6},~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19},~{v20},~{v21},~{v22},~{v23},~{v24},~{v25},~{v26},~{v27},~{v28},~{v29},~{v30},~{v31}"()
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134 tail call void @llvm.aarch64.neon.st4.v16i8.p0i8(<16 x i8> %vec0, <16 x i8> %vec1, <16 x i8> %vec2, <16 x i8> %vec3, i8* %addr)
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135 ret void
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136 }
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137
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138 declare { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2.v8i8.p0v8i8(<8 x i8>*)
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139 declare { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3.v8i8.p0v8i8(<8 x i8>*)
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140 declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3.v16i8.p0v16i8(<16 x i8>*)
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141 declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4.v16i8.p0v16i8(<16 x i8>*)
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142
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143 declare void @llvm.aarch64.neon.st2.v8i8.p0i8(<8 x i8>, <8 x i8>, i8*)
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144 declare void @llvm.aarch64.neon.st3.v8i8.p0i8(<8 x i8>, <8 x i8>, <8 x i8>, i8*)
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145 declare void @llvm.aarch64.neon.st3.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, i8*)
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146 declare void @llvm.aarch64.neon.st4.v16i8.p0i8(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i8*)