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annotate test/CodeGen/AArch64/arm64-vbitwise.ll @ 100:7d135dc70f03 LLVM 3.9

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children 1172e4bd9c6f
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1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
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2
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3 define <8 x i8> @rbit_8b(<8 x i8>* %A) nounwind {
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4 ;CHECK-LABEL: rbit_8b:
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5 ;CHECK: rbit.8b
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6 %tmp1 = load <8 x i8>, <8 x i8>* %A
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7 %tmp3 = call <8 x i8> @llvm.aarch64.neon.rbit.v8i8(<8 x i8> %tmp1)
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8 ret <8 x i8> %tmp3
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9 }
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10
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11 define <16 x i8> @rbit_16b(<16 x i8>* %A) nounwind {
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12 ;CHECK-LABEL: rbit_16b:
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13 ;CHECK: rbit.16b
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14 %tmp1 = load <16 x i8>, <16 x i8>* %A
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15 %tmp3 = call <16 x i8> @llvm.aarch64.neon.rbit.v16i8(<16 x i8> %tmp1)
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16 ret <16 x i8> %tmp3
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17 }
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18
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19 declare <8 x i8> @llvm.aarch64.neon.rbit.v8i8(<8 x i8>) nounwind readnone
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20 declare <16 x i8> @llvm.aarch64.neon.rbit.v16i8(<16 x i8>) nounwind readnone
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21
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22 define <8 x i16> @sxtl8h(<8 x i8>* %A) nounwind {
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23 ;CHECK-LABEL: sxtl8h:
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24 ;CHECK: sshll.8h
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25 %tmp1 = load <8 x i8>, <8 x i8>* %A
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26 %tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
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27 ret <8 x i16> %tmp2
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28 }
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29
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30 define <8 x i16> @uxtl8h(<8 x i8>* %A) nounwind {
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31 ;CHECK-LABEL: uxtl8h:
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32 ;CHECK: ushll.8h
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33 %tmp1 = load <8 x i8>, <8 x i8>* %A
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34 %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
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35 ret <8 x i16> %tmp2
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36 }
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37
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38 define <4 x i32> @sxtl4s(<4 x i16>* %A) nounwind {
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39 ;CHECK-LABEL: sxtl4s:
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40 ;CHECK: sshll.4s
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41 %tmp1 = load <4 x i16>, <4 x i16>* %A
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42 %tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
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43 ret <4 x i32> %tmp2
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44 }
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45
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46 define <4 x i32> @uxtl4s(<4 x i16>* %A) nounwind {
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47 ;CHECK-LABEL: uxtl4s:
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48 ;CHECK: ushll.4s
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49 %tmp1 = load <4 x i16>, <4 x i16>* %A
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50 %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
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51 ret <4 x i32> %tmp2
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52 }
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53
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54 define <2 x i64> @sxtl2d(<2 x i32>* %A) nounwind {
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55 ;CHECK-LABEL: sxtl2d:
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56 ;CHECK: sshll.2d
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57 %tmp1 = load <2 x i32>, <2 x i32>* %A
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58 %tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
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59 ret <2 x i64> %tmp2
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60 }
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61
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62 define <2 x i64> @uxtl2d(<2 x i32>* %A) nounwind {
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63 ;CHECK-LABEL: uxtl2d:
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64 ;CHECK: ushll.2d
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65 %tmp1 = load <2 x i32>, <2 x i32>* %A
77
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66 %tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
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67 ret <2 x i64> %tmp2
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68 }
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69
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70 ; Check for incorrect use of vector bic.
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71 ; rdar://11553859
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72 define void @test_vsliq(i8* nocapture %src, i8* nocapture %dest) nounwind noinline ssp {
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73 entry:
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74 ; CHECK-LABEL: test_vsliq:
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75 ; CHECK-NOT: bic
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76 ; CHECK: movi.2d [[REG1:v[0-9]+]], #0x0000ff000000ff
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77 ; CHECK: and.16b v{{[0-9]+}}, v{{[0-9]+}}, [[REG1]]
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78 %0 = bitcast i8* %src to <16 x i8>*
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79 %1 = load <16 x i8>, <16 x i8>* %0, align 16
77
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80 %and.i = and <16 x i8> %1, <i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 0, i8 0>
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81 %2 = bitcast <16 x i8> %and.i to <8 x i16>
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82 %vshl_n = shl <8 x i16> %2, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
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83 %3 = or <8 x i16> %2, %vshl_n
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84 %4 = bitcast <8 x i16> %3 to <4 x i32>
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85 %vshl_n8 = shl <4 x i32> %4, <i32 16, i32 16, i32 16, i32 16>
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86 %5 = or <4 x i32> %4, %vshl_n8
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87 %6 = bitcast <4 x i32> %5 to <16 x i8>
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88 %7 = bitcast i8* %dest to <16 x i8>*
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89 store <16 x i8> %6, <16 x i8>* %7, align 16
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90 ret void
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91 }