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annotate test/CodeGen/AArch64/arm64-vcnt.ll @ 100:7d135dc70f03 LLVM 3.9

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children 1172e4bd9c6f
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1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
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2
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3 define <8 x i8> @cls_8b(<8 x i8>* %A) nounwind {
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4 ;CHECK-LABEL: cls_8b:
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5 ;CHECK: cls.8b
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6 %tmp1 = load <8 x i8>, <8 x i8>* %A
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7 %tmp3 = call <8 x i8> @llvm.aarch64.neon.cls.v8i8(<8 x i8> %tmp1)
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8 ret <8 x i8> %tmp3
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9 }
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10
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11 define <16 x i8> @cls_16b(<16 x i8>* %A) nounwind {
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12 ;CHECK-LABEL: cls_16b:
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13 ;CHECK: cls.16b
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14 %tmp1 = load <16 x i8>, <16 x i8>* %A
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15 %tmp3 = call <16 x i8> @llvm.aarch64.neon.cls.v16i8(<16 x i8> %tmp1)
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16 ret <16 x i8> %tmp3
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17 }
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18
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19 define <4 x i16> @cls_4h(<4 x i16>* %A) nounwind {
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20 ;CHECK-LABEL: cls_4h:
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21 ;CHECK: cls.4h
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22 %tmp1 = load <4 x i16>, <4 x i16>* %A
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23 %tmp3 = call <4 x i16> @llvm.aarch64.neon.cls.v4i16(<4 x i16> %tmp1)
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24 ret <4 x i16> %tmp3
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25 }
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26
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27 define <8 x i16> @cls_8h(<8 x i16>* %A) nounwind {
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28 ;CHECK-LABEL: cls_8h:
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29 ;CHECK: cls.8h
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30 %tmp1 = load <8 x i16>, <8 x i16>* %A
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31 %tmp3 = call <8 x i16> @llvm.aarch64.neon.cls.v8i16(<8 x i16> %tmp1)
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32 ret <8 x i16> %tmp3
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33 }
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34
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35 define <2 x i32> @cls_2s(<2 x i32>* %A) nounwind {
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36 ;CHECK-LABEL: cls_2s:
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37 ;CHECK: cls.2s
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38 %tmp1 = load <2 x i32>, <2 x i32>* %A
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39 %tmp3 = call <2 x i32> @llvm.aarch64.neon.cls.v2i32(<2 x i32> %tmp1)
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40 ret <2 x i32> %tmp3
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41 }
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42
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43 define <4 x i32> @cls_4s(<4 x i32>* %A) nounwind {
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44 ;CHECK-LABEL: cls_4s:
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45 ;CHECK: cls.4s
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46 %tmp1 = load <4 x i32>, <4 x i32>* %A
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47 %tmp3 = call <4 x i32> @llvm.aarch64.neon.cls.v4i32(<4 x i32> %tmp1)
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48 ret <4 x i32> %tmp3
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49 }
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51 declare <8 x i8> @llvm.aarch64.neon.cls.v8i8(<8 x i8>) nounwind readnone
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52 declare <16 x i8> @llvm.aarch64.neon.cls.v16i8(<16 x i8>) nounwind readnone
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53 declare <4 x i16> @llvm.aarch64.neon.cls.v4i16(<4 x i16>) nounwind readnone
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54 declare <8 x i16> @llvm.aarch64.neon.cls.v8i16(<8 x i16>) nounwind readnone
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55 declare <2 x i32> @llvm.aarch64.neon.cls.v2i32(<2 x i32>) nounwind readnone
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56 declare <4 x i32> @llvm.aarch64.neon.cls.v4i32(<4 x i32>) nounwind readnone