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annotate test/CodeGen/AArch64/concat_vector-truncate-combine.ll @ 100:7d135dc70f03 LLVM 3.9

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children
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1 ; RUN: llc < %s -mtriple arm64-apple-darwin -asm-verbose=false | FileCheck %s
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2
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3 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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4
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5 ; Test the (concat_vectors (trunc), (trunc)) pattern.
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6
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7 define <4 x i16> @test_concat_truncate_v2i64_to_v4i16(<2 x i64> %a, <2 x i64> %b) #0 {
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8 entry:
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9 ; CHECK-LABEL: test_concat_truncate_v2i64_to_v4i16:
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10 ; CHECK-NEXT: uzp1.4s v0, v0, v1
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11 ; CHECK-NEXT: xtn.4h v0, v0
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12 ; CHECK-NEXT: ret
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13 %at = trunc <2 x i64> %a to <2 x i16>
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14 %bt = trunc <2 x i64> %b to <2 x i16>
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15 %shuffle = shufflevector <2 x i16> %at, <2 x i16> %bt, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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16 ret <4 x i16> %shuffle
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17 }
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18
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19 define <8 x i8> @test_concat_truncate_v4i32_to_v8i8(<4 x i32> %a, <4 x i32> %b) #0 {
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20 entry:
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21 ; CHECK-LABEL: test_concat_truncate_v4i32_to_v8i8:
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22 ; CHECK-NEXT: uzp1.8h v0, v0, v1
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23 ; CHECK-NEXT: xtn.8b v0, v0
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24 ; CHECK-NEXT: ret
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25 %at = trunc <4 x i32> %a to <4 x i8>
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26 %bt = trunc <4 x i32> %b to <4 x i8>
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27 %shuffle = shufflevector <4 x i8> %at, <4 x i8> %bt, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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28 ret <8 x i8> %shuffle
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29 }
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30
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31 define <8 x i16> @test_concat_truncate_v4i32_to_v8i16(<4 x i32> %a, <4 x i32> %b) #0 {
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32 entry:
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33 ; CHECK-LABEL: test_concat_truncate_v4i32_to_v8i16:
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34 ; CHECK-NEXT: xtn.4h v0, v0
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35 ; CHECK-NEXT: xtn2.8h v0, v1
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36 ; CHECK-NEXT: ret
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37 %at = trunc <4 x i32> %a to <4 x i16>
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38 %bt = trunc <4 x i32> %b to <4 x i16>
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39 %shuffle = shufflevector <4 x i16> %at, <4 x i16> %bt, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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40 ret <8 x i16> %shuffle
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41 }
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42
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43 attributes #0 = { nounwind }