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annotate test/CodeGen/AMDGPU/llvm.SI.fs.interp.ll @ 100:7d135dc70f03 LLVM 3.9

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children 1172e4bd9c6f
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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1 ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s
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2 ;RUN: llc < %s -march=amdgcn -mcpu=kabini -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=16BANK %s
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3 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s
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4
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5 ;GCN-LABEL: {{^}}main:
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6 ;GCN-NOT: s_wqm
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7 ;GCN: s_mov_b32
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8 ;GCN-NEXT: v_interp_mov_f32
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9 ;GCN: v_interp_p1_f32
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10 ;GCN: v_interp_p2_f32
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11
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12 define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>) #0 {
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13 main_body:
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14 %5 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
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15 %6 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %4)
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16 %7 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %4)
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17 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %5, float %6, float %7, float %7)
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18 ret void
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19 }
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20
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21 ; Thest that v_interp_p1 uses different source and destination registers
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22 ; on 16 bank LDS chips.
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23
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24 ; 16BANK-LABEL: {{^}}v_interp_p1_bank16_bug:
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25 ; 16BANK-NOT: v_interp_p1_f32 [[DST:v[0-9]+]], [[DST]]
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26
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27 define void @v_interp_p1_bank16_bug([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #0 {
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28 main_body:
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29 %22 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7)
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30 %23 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7)
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31 %24 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7)
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32 %25 = call float @fabs(float %22)
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33 %26 = call float @fabs(float %23)
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34 %27 = call float @fabs(float %24)
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35 %28 = call i32 @llvm.SI.packf16(float %25, float %26)
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36 %29 = bitcast i32 %28 to float
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37 %30 = call i32 @llvm.SI.packf16(float %27, float 1.000000e+00)
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38 %31 = bitcast i32 %30 to float
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39 call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %29, float %31, float %29, float %31)
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40 ret void
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41 }
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42
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43 ; Function Attrs: readnone
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44 declare float @fabs(float) #2
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45
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46 ; Function Attrs: nounwind readnone
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47 declare i32 @llvm.SI.packf16(float, float) #1
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48
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49 ; Function Attrs: nounwind readnone
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50 declare float @llvm.SI.fs.constant(i32, i32, i32) #1
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51
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52 ; Function Attrs: nounwind readnone
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53 declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #1
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54
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55 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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56
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57 attributes #0 = { "ShaderType"="0" }
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58 attributes #1 = { nounwind readnone }
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59 attributes #2 = { readnone }