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annotate test/CodeGen/AMDGPU/mad_int24.ll @ 100:7d135dc70f03 LLVM 3.9

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children 1172e4bd9c6f
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54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC
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2 ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM --check-prefix=FUNC
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3 ; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC
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4 ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC
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6 declare i32 @llvm.AMDGPU.imul24(i32, i32) nounwind readnone
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7
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8 ; FUNC-LABEL: {{^}}i32_mad24:
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9 ; Signed 24-bit multiply is not supported on pre-Cayman GPUs.
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10 ; EG: MULLO_INT
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11 ; Make sure we aren't masking the inputs.
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12 ; CM-NOT: AND
54457678186b LLVM 3.6
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13 ; CM: MULADD_INT24
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14 ; SI-NOT: and
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15 ; SI: v_mad_i32_i24
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16 define void @i32_mad24(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
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17 entry:
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18 %0 = shl i32 %a, 8
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19 %a_24 = ashr i32 %0, 8
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20 %1 = shl i32 %b, 8
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21 %b_24 = ashr i32 %1, 8
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22 %2 = mul i32 %a_24, %b_24
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23 %3 = add i32 %2, %c
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24 store i32 %3, i32 addrspace(1)* %out
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25 ret void
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26 }
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28 ; FUNC-LABEL: @test_imul24
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29 ; SI: v_mad_i32_i24
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30 define void @test_imul24(i32 addrspace(1)* %out, i32 %src0, i32 %src1, i32 %src2) nounwind {
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31 %mul = call i32 @llvm.AMDGPU.imul24(i32 %src0, i32 %src1) nounwind readnone
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32 %add = add i32 %mul, %src2
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33 store i32 %add, i32 addrspace(1)* %out, align 4
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34 ret void
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35 }