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annotate test/CodeGen/AMDGPU/mad_uint24.ll @ 100:7d135dc70f03 LLVM 3.9

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children 1172e4bd9c6f
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC
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2 ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG --check-prefix=FUNC
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3 ; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC
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4 ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=SI --check-prefix=FUNC
0
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5
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6 ; FUNC-LABEL: {{^}}u32_mad24:
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7 ; EG: MULADD_UINT24
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8 ; SI: v_mad_u32_u24
0
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9
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10 define void @u32_mad24(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
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11 entry:
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12 %0 = shl i32 %a, 8
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13 %a_24 = lshr i32 %0, 8
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14 %1 = shl i32 %b, 8
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15 %b_24 = lshr i32 %1, 8
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16 %2 = mul i32 %a_24, %b_24
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17 %3 = add i32 %2, %c
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18 store i32 %3, i32 addrspace(1)* %out
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19 ret void
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20 }
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21
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22 ; FUNC-LABEL: {{^}}i16_mad24:
0
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23 ; The order of A and B does not matter.
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24 ; EG: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]]
0
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25 ; The result must be sign-extended
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26 ; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x
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27 ; EG: 16
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28 ; SI: v_mad_u32_u24 [[MAD:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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29 ; SI: v_bfe_i32 v{{[0-9]}}, [[MAD]], 0, 16
0
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30
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31 define void @i16_mad24(i32 addrspace(1)* %out, i16 %a, i16 %b, i16 %c) {
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32 entry:
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33 %0 = mul i16 %a, %b
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34 %1 = add i16 %0, %c
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35 %2 = sext i16 %1 to i32
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36 store i32 %2, i32 addrspace(1)* %out
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37 ret void
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38 }
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39
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40 ; FUNC-LABEL: {{^}}i8_mad24:
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41 ; EG: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]]
0
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42 ; The result must be sign-extended
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43 ; EG: BFE_INT {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[MAD_CHAN]], 0.0, literal.x
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44 ; EG: 8
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45 ; SI: v_mad_u32_u24 [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
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46 ; SI: v_bfe_i32 v{{[0-9]}}, [[MUL]], 0, 8
0
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47
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48 define void @i8_mad24(i32 addrspace(1)* %out, i8 %a, i8 %b, i8 %c) {
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49 entry:
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50 %0 = mul i8 %a, %b
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51 %1 = add i8 %0, %c
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52 %2 = sext i8 %1 to i32
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53 store i32 %2, i32 addrspace(1)* %out
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54 ret void
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55 }
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57 ; This tests for a bug where the mad_u24 pattern matcher would call
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
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58 ; SimplifyDemandedBits on the first operand of the mul instruction
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
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59 ; assuming that the pattern would be matched to a 24-bit mad. This
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60 ; led to some instructions being incorrectly erased when the entire
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61 ; 24-bit mad pattern wasn't being matched.
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62
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63 ; Check that the select instruction is not deleted.
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64 ; FUNC-LABEL: {{^}}i24_i32_i32_mad:
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65 ; EG: CNDE_INT
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66 ; SI: v_cndmask
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67 define void @i24_i32_i32_mad(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c, i32 %d) {
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68 entry:
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69 %0 = ashr i32 %a, 8
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70 %1 = icmp ne i32 %c, 0
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71 %2 = select i1 %1, i32 %0, i32 34
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72 %3 = mul i32 %2, %c
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73 %4 = add i32 %3, %d
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74 store i32 %4, i32 addrspace(1)* %out
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75 ret void
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76 }