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annotate test/CodeGen/AMDGPU/vop-shrink.ll @ 100:7d135dc70f03 LLVM 3.9

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children 1172e4bd9c6f
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afa8332a0e37 LLVM 3.8
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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3
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4 ; Test that we correctly commute a sub instruction
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5 ; FUNC-LABEL: {{^}}sub_rev:
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6 ; SI-NOT: v_sub_i32_e32 v{{[0-9]+}}, vcc, s
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7 ; SI: v_subrev_i32_e32 v{{[0-9]+}}, vcc, s
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8
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9 ; ModuleID = 'vop-shrink.ll'
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10
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11 define void @sub_rev(i32 addrspace(1)* %out, <4 x i32> %sgpr, i32 %cond) {
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12 entry:
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13 %vgpr = call i32 @llvm.r600.read.tidig.x() #1
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14 %tmp = icmp eq i32 %cond, 0
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15 br i1 %tmp, label %if, label %else
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16
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17 if: ; preds = %entry
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18 %tmp1 = getelementptr i32, i32 addrspace(1)* %out, i32 1
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19 %tmp2 = extractelement <4 x i32> %sgpr, i32 1
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20 store i32 %tmp2, i32 addrspace(1)* %out
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21 br label %endif
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22
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23 else: ; preds = %entry
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24 %tmp3 = extractelement <4 x i32> %sgpr, i32 2
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25 %tmp4 = sub i32 %vgpr, %tmp3
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26 store i32 %tmp4, i32 addrspace(1)* %out
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27 br label %endif
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28
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29 endif: ; preds = %else, %if
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30 ret void
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31 }
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32
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33 ; Test that we fold an immediate that was illegal for a 64-bit op into the
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34 ; 32-bit op when we shrink it.
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35
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36 ; FUNC-LABEL: {{^}}add_fold:
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37 ; SI: v_add_f32_e32 v{{[0-9]+}}, 0x44800000
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38 define void @add_fold(float addrspace(1)* %out) {
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39 entry:
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40 %tmp = call i32 @llvm.r600.read.tidig.x()
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41 %tmp1 = uitofp i32 %tmp to float
afa8332a0e37 LLVM 3.8
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42 %tmp2 = fadd float %tmp1, 1.024000e+03
afa8332a0e37 LLVM 3.8
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43 store float %tmp2, float addrspace(1)* %out
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44 ret void
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45 }
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46
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47 ; Function Attrs: nounwind readnone
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48 declare i32 @llvm.r600.read.tidig.x() #0
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49
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50 attributes #0 = { nounwind readnone }
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51 attributes #1 = { readnone }