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annotate test/CodeGen/PowerPC/vec-abi-align.ll @ 100:7d135dc70f03 LLVM 3.9

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children 1172e4bd9c6f
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx < %s | FileCheck %s
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2 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s
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3 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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4 target triple = "powerpc64-unknown-linux-gnu"
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5
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6 %struct.s2 = type { i64, <4 x float> }
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7
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8 @ve = external global <4 x float>
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9 @n = external global i64
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10
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11 ; Function Attrs: nounwind
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12 define void @test1(i64 %d1, i64 %d2, i64 %d3, i64 %d4, i64 %d5, i64 %d6, i64 %d7, i64 %d8, i64 %d9, <4 x float> inreg %vs.coerce) #0 {
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13 entry:
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14 store <4 x float> %vs.coerce, <4 x float>* @ve, align 16
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15 ret void
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16
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17 ; CHECK-LABEL: @test1
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18 ; CHECK: stvx 2,
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19 ; CHECK: blr
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20
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21 ; CHECK-VSX-LABEL: @test1
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22 ; CHECK-VSX: stxvw4x 34,
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23 ; CHECK-VSX: blr
0
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24 }
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25
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26 ; Function Attrs: nounwind
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27 define void @test2(i64 %d1, i64 %d2, i64 %d3, i64 %d4, i64 %d5, i64 %d6, i64 %d7, i64 %d8, %struct.s2* byval nocapture readonly %vs) #0 {
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28 entry:
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29 %m = getelementptr inbounds %struct.s2, %struct.s2* %vs, i64 0, i32 0
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30 %0 = load i64, i64* %m, align 8
0
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31 store i64 %0, i64* @n, align 8
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32 %v = getelementptr inbounds %struct.s2, %struct.s2* %vs, i64 0, i32 1
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33 %1 = load <4 x float>, <4 x float>* %v, align 16
0
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34 store <4 x float> %1, <4 x float>* @ve, align 16
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35 ret void
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36
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37 ; CHECK-LABEL: @test2
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38 ; CHECK-DAG: ld {{[0-9]+}}, 112(1)
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39 ; CHECK-DAG: li [[REG16:[0-9]+]], 16
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40 ; CHECK-DAG: addi [[REGB:[0-9]+]], 1, 112
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41 ; CHECK-DAG: lvx 2, [[REGB]], [[REG16]]
0
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42 ; CHECK: blr
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43
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44 ; CHECK-VSX-LABEL: @test2
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45 ; CHECK-VSX-DAG: ld {{[0-9]+}}, 112(1)
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46 ; CHECK-VSX-DAG: li [[REG16:[0-9]+]], 16
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47 ; CHECK-VSX-DAG: addi [[REGB:[0-9]+]], 1, 112
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48 ; CHECK-VSX-DAG: lxvw4x {{[0-9]+}}, [[REGB]], [[REG16]]
83
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49 ; CHECK-VSX: blr
0
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50 }
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51
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52 ; Function Attrs: nounwind
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53 define void @test3(i64 %d1, i64 %d2, i64 %d3, i64 %d4, i64 %d5, i64 %d6, i64 %d7, i64 %d8, i64 %d9, %struct.s2* byval nocapture readonly %vs) #0 {
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54 entry:
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55 %m = getelementptr inbounds %struct.s2, %struct.s2* %vs, i64 0, i32 0
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56 %0 = load i64, i64* %m, align 8
0
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57 store i64 %0, i64* @n, align 8
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58 %v = getelementptr inbounds %struct.s2, %struct.s2* %vs, i64 0, i32 1
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59 %1 = load <4 x float>, <4 x float>* %v, align 16
0
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60 store <4 x float> %1, <4 x float>* @ve, align 16
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61 ret void
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62
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63 ; CHECK-LABEL: @test3
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64 ; CHECK-DAG: ld {{[0-9]+}}, 128(1)
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65 ; CHECK-DAG: li [[REG16:[0-9]+]], 16
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66 ; CHECK-DAG: addi [[REGB:[0-9]+]], 1, 128
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67 ; CHECK-DAG: lvx 2, [[REGB]], [[REG16]]
0
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68 ; CHECK: blr
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69
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70 ; CHECK-VSX-LABEL: @test3
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71 ; CHECK-VSX-DAG: ld {{[0-9]+}}, 128(1)
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72 ; CHECK-VSX-DAG: li [[REG16:[0-9]+]], 16
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73 ; CHECK-VSX-DAG: addi [[REGB:[0-9]+]], 1, 128
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74 ; CHECK-VSX-DAG: lxvw4x {{[0-9]+}}, [[REGB]], [[REG16]]
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75 ; CHECK-VSX: blr
0
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76 }
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77
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78 attributes #0 = { nounwind }
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79