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annotate test/CodeGen/PowerPC/vec_perf_shuffle.ll @ 100:7d135dc70f03 LLVM 3.9

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children 1172e4bd9c6f
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1 ; RUN: llc < %s -march=ppc32 -mcpu=g5 | not grep vperm
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3 define <4 x float> @test_uu72(<4 x float>* %P1, <4 x float>* %P2) {
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4 %V1 = load <4 x float>, <4 x float>* %P1 ; <<4 x float>> [#uses=1]
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5 %V2 = load <4 x float>, <4 x float>* %P2 ; <<4 x float>> [#uses=1]
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6 %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 undef, i32 undef, i32 7, i32 2 > ; <<4 x float>> [#uses=1]
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7 ret <4 x float> %V3
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8 }
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10 define <4 x float> @test_30u5(<4 x float>* %P1, <4 x float>* %P2) {
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11 %V1 = load <4 x float>, <4 x float>* %P1 ; <<4 x float>> [#uses=1]
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12 %V2 = load <4 x float>, <4 x float>* %P2 ; <<4 x float>> [#uses=1]
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13 %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 0, i32 undef, i32 5 > ; <<4 x float>> [#uses=1]
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14 ret <4 x float> %V3
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15 }
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17 define <4 x float> @test_3u73(<4 x float>* %P1, <4 x float>* %P2) {
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18 %V1 = load <4 x float>, <4 x float>* %P1 ; <<4 x float>> [#uses=1]
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19 %V2 = load <4 x float>, <4 x float>* %P2 ; <<4 x float>> [#uses=1]
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20 %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 undef, i32 7, i32 3 > ; <<4 x float>> [#uses=1]
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21 ret <4 x float> %V3
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22 }
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24 define <4 x float> @test_3774(<4 x float>* %P1, <4 x float>* %P2) {
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25 %V1 = load <4 x float>, <4 x float>* %P1 ; <<4 x float>> [#uses=1]
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26 %V2 = load <4 x float>, <4 x float>* %P2 ; <<4 x float>> [#uses=1]
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27 %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 3, i32 7, i32 7, i32 4 > ; <<4 x float>> [#uses=1]
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28 ret <4 x float> %V3
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29 }
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31 define <4 x float> @test_4450(<4 x float>* %P1, <4 x float>* %P2) {
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32 %V1 = load <4 x float>, <4 x float>* %P1 ; <<4 x float>> [#uses=1]
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33 %V2 = load <4 x float>, <4 x float>* %P2 ; <<4 x float>> [#uses=1]
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34 %V3 = shufflevector <4 x float> %V1, <4 x float> %V2, <4 x i32> < i32 4, i32 4, i32 5, i32 0 > ; <<4 x float>> [#uses=1]
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35 ret <4 x float> %V3
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36 }