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annotate test/CodeGen/X86/2006-05-17-VectorArg.ll @ 100:7d135dc70f03 LLVM 3.9

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents 95c75e76d11b
children 803732b1fca8
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95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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1 ; RUN: llc < %s -march=x86 -mattr=+sse2
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3 define <4 x float> @opRSQ(<4 x float> %a) nounwind {
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4 entry:
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5 %tmp2 = extractelement <4 x float> %a, i32 3 ; <float> [#uses=2]
95c75e76d11b LLVM 3.4
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6 %abscond = fcmp oge float %tmp2, -0.000000e+00 ; <i1> [#uses=1]
95c75e76d11b LLVM 3.4
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7 %abs = select i1 %abscond, float %tmp2, float 0.000000e+00 ; <float> [#uses=1]
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8 %tmp3 = tail call float @llvm.sqrt.f32( float %abs ) ; <float> [#uses=1]
95c75e76d11b LLVM 3.4
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9 %tmp4 = fdiv float 1.000000e+00, %tmp3 ; <float> [#uses=1]
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10 %tmp11 = insertelement <4 x float> zeroinitializer, float %tmp4, i32 3 ; <<4 x float>> [#uses=1]
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11 ret <4 x float> %tmp11
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12 }
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14 declare float @llvm.sqrt.f32(float)
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