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annotate test/CodeGen/X86/SwizzleShuff.ll @ 100:7d135dc70f03 LLVM 3.9

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LLVM 3.9
author Miyagi Mitsuki <e135756@ie.u-ryukyu.ac.jp>
date Tue, 26 Jan 2016 22:53:40 +0900
parents afa8332a0e37
children 803732b1fca8
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77
54457678186b LLVM 3.6
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 0
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1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx -x86-experimental-vector-widening-legalization | FileCheck %s
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2
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3 ; Check that we perform a scalar XOR on i32.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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4
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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5 ; CHECK: pull_bitcast
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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6 ; CHECK: xorl
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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7 ; CHECK: ret
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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8 define void @pull_bitcast (<4 x i8>* %pA, <4 x i8>* %pB) {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
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9 %A = load <4 x i8>, <4 x i8>* %pA
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parents: 83
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10 %B = load <4 x i8>, <4 x i8>* %pB
0
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11 %C = xor <4 x i8> %A, %B
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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12 store <4 x i8> %C, <4 x i8>* %pA
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13 ret void
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14 }
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15
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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16 ; CHECK: multi_use_swizzle
83
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
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17 ; CHECK: pshufd
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
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18 ; CHECK-NEXT: pshufd
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
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19 ; CHECK-NEXT: pblendw
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
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20 ; CHECK-NEXT: pshufd
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
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21 ; CHECK-NEXT: pshufd
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
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22 ; CHECK-NEXT: pxor
0
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23 ; CHECK-NEXT: ret
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24 define <4 x i32> @multi_use_swizzle (<4 x i32>* %pA, <4 x i32>* %pB) {
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25 %A = load <4 x i32>, <4 x i32>* %pA
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26 %B = load <4 x i32>, <4 x i32>* %pB
0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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27 %S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 1, i32 5, i32 6>
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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28 %S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 1, i32 3, i32 2, i32 2>
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29 %S2 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 2, i32 1, i32 0, i32 2>
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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30 %R = xor <4 x i32> %S1, %S2
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31 ret <4 x i32> %R
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32 }
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33
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34 ; CHECK: pull_bitcast2
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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35 ; CHECK: xorl
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36 ; CHECK: ret
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37 define <4 x i8> @pull_bitcast2 (<4 x i8>* %pA, <4 x i8>* %pB, <4 x i8>* %pC) {
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parents: 83
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38 %A = load <4 x i8>, <4 x i8>* %pA
0
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39 store <4 x i8> %A, <4 x i8>* %pC
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
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40 %B = load <4 x i8>, <4 x i8>* %pB
0
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41 %C = xor <4 x i8> %A, %B
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42 store <4 x i8> %C, <4 x i8>* %pA
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43 ret <4 x i8> %C
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44 }
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45
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46
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47
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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48 ; CHECK: reverse_1
83
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
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49 ; CHECK-NOT: pshufd
0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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50 ; CHECK: ret
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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51 define <4 x i32> @reverse_1 (<4 x i32>* %pA, <4 x i32>* %pB) {
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parents: 83
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52 %A = load <4 x i32>, <4 x i32>* %pA
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parents: 83
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53 %B = load <4 x i32>, <4 x i32>* %pB
0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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54 %S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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55 %S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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56 ret <4 x i32> %S1
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57 }
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58
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59
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60 ; CHECK: no_reverse_shuff
83
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Tatsuki IHA <e125716@ie.u-ryukyu.ac.jp>
parents: 77
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61 ; CHECK: pshufd
0
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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62 ; CHECK: ret
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63 define <4 x i32> @no_reverse_shuff (<4 x i32>* %pA, <4 x i32>* %pB) {
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64 %A = load <4 x i32>, <4 x i32>* %pA
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents: 83
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65 %B = load <4 x i32>, <4 x i32>* %pB
0
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parents:
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66 %S = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
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67 %S1 = shufflevector <4 x i32> %S, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 2>
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68 ret <4 x i32> %S1
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parents:
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69 }