CbC/CbC_llvm: lib/Target/Hexagon/HexagonExpandCondsets.cpp annotate

annotate lib/Target/Hexagon/HexagonExpandCondsets.cpp @ 121:803732b1fca8

LLVM 5.0

author	kono
date	Fri, 27 Oct 2017 17:07:41 +0900
parents	1172e4bd9c6f
children	3a76565eade5

rev	line source
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	1 //===- HexagonExpandCondsets.cpp ------------------------------------------===//
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	2 //
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	3 // The LLVM Compiler Infrastructure
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	4 //
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	5 // This file is distributed under the University of Illinois Open Source
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	6 // License. See LICENSE.TXT for details.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	7 //
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	8 //===----------------------------------------------------------------------===//
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	9
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	10 // Replace mux instructions with the corresponding legal instructions.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	11 // It is meant to work post-SSA, but still on virtual registers. It was
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	12 // originally placed between register coalescing and machine instruction
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	13 // scheduler.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	14 // In this place in the optimization sequence, live interval analysis had
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	15 // been performed, and the live intervals should be preserved. A large part
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	16 // of the code deals with preserving the liveness information.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	17 //
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	18 // Liveness tracking aside, the main functionality of this pass is divided
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	19 // into two steps. The first step is to replace an instruction
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	20 // vreg0 = C2_mux vreg1, vreg2, vreg3
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	21 // with a pair of conditional transfers
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	22 // vreg0 = A2_tfrt vreg1, vreg2
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	23 // vreg0 = A2_tfrf vreg1, vreg3
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	24 // It is the intention that the execution of this pass could be terminated
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	25 // after this step, and the code generated would be functionally correct.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	26 //
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	27 // If the uses of the source values vreg1 and vreg2 are kills, and their
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	28 // definitions are predicable, then in the second step, the conditional
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	29 // transfers will then be rewritten as predicated instructions. E.g.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	30 // vreg0 = A2_or vreg1, vreg2
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	31 // vreg3 = A2_tfrt vreg99, vreg0<kill>
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	32 // will be rewritten as
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	33 // vreg3 = A2_port vreg99, vreg1, vreg2
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	34 //
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	35 // This replacement has two variants: "up" and "down". Consider this case:
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	36 // vreg0 = A2_or vreg1, vreg2
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	37 // ... [intervening instructions] ...
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	38 // vreg3 = A2_tfrt vreg99, vreg0<kill>
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	39 // variant "up":
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	40 // vreg3 = A2_port vreg99, vreg1, vreg2
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	41 // ... [intervening instructions, vreg0->vreg3] ...
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	42 // [deleted]
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	43 // variant "down":
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	44 // [deleted]
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	45 // ... [intervening instructions] ...
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	46 // vreg3 = A2_port vreg99, vreg1, vreg2
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	47 //
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	48 // Both, one or none of these variants may be valid, and checks are made
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	49 // to rule out inapplicable variants.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	50 //
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	51 // As an additional optimization, before either of the two steps above is
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	52 // executed, the pass attempts to coalesce the target register with one of
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	53 // the source registers, e.g. given an instruction
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	54 // vreg3 = C2_mux vreg0, vreg1, vreg2
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	55 // vreg3 will be coalesced with either vreg1 or vreg2. If this succeeds,
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	56 // the instruction would then be (for example)
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	57 // vreg3 = C2_mux vreg0, vreg3, vreg2
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	58 // and, under certain circumstances, this could result in only one predicated
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	59 // instruction:
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	60 // vreg3 = A2_tfrf vreg0, vreg2
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	61 //
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	62
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	63 // Splitting a definition of a register into two predicated transfers
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	64 // creates a complication in liveness tracking. Live interval computation
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	65 // will see both instructions as actual definitions, and will mark the
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	66 // first one as dead. The definition is not actually dead, and this
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	67 // situation will need to be fixed. For example:
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	68 // vreg1<def,dead> = A2_tfrt ... ; marked as dead
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	69 // vreg1<def> = A2_tfrf ...
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	70 //
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	71 // Since any of the individual predicated transfers may end up getting
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	72 // removed (in case it is an identity copy), some pre-existing def may
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	73 // be marked as dead after live interval recomputation:
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	74 // vreg1<def,dead> = ... ; marked as dead
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	75 // ...
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	76 // vreg1<def> = A2_tfrf ... ; if A2_tfrt is removed
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	77 // This case happens if vreg1 was used as a source in A2_tfrt, which means
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	78 // that is it actually live at the A2_tfrf, and so the now dead definition
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	79 // of vreg1 will need to be updated to non-dead at some point.
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	80 //
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	81 // This issue could be remedied by adding implicit uses to the predicated
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	82 // transfers, but this will create a problem with subsequent predication,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	83 // since the transfers will no longer be possible to reorder. To avoid
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	84 // that, the initial splitting will not add any implicit uses. These
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	85 // implicit uses will be added later, after predication. The extra price,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	86 // however, is that finding the locations where the implicit uses need
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	87 // to be added, and updating the live ranges will be more involved.
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	88
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	89 #include "HexagonInstrInfo.h"
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	90 #include "HexagonRegisterInfo.h"
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	91 #include "llvm/ADT/DenseMap.h"
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	92 #include "llvm/ADT/SetVector.h"
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	93 #include "llvm/ADT/SmallVector.h"
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	94 #include "llvm/ADT/StringRef.h"
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	95 #include "llvm/CodeGen/LiveInterval.h"
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	96 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	97 #include "llvm/CodeGen/MachineBasicBlock.h"
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	98 #include "llvm/CodeGen/MachineDominators.h"
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	99 #include "llvm/CodeGen/MachineFunction.h"
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	100 #include "llvm/CodeGen/MachineFunctionPass.h"
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	101 #include "llvm/CodeGen/MachineInstr.h"
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	102 #include "llvm/CodeGen/MachineInstrBuilder.h"
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	103 #include "llvm/CodeGen/MachineOperand.h"
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	104 #include "llvm/CodeGen/MachineRegisterInfo.h"
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	105 #include "llvm/CodeGen/SlotIndexes.h"
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	106 #include "llvm/IR/DebugLoc.h"
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	107 #include "llvm/IR/Function.h"
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	108 #include "llvm/MC/LaneBitmask.h"
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	109 #include "llvm/Pass.h"
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	110 #include "llvm/Support/CommandLine.h"
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	111 #include "llvm/Support/Debug.h"
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	112 #include "llvm/Support/ErrorHandling.h"
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	113 #include "llvm/Support/raw_ostream.h"
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	114 #include "llvm/Target/TargetRegisterInfo.h"
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	115 #include "llvm/Target/TargetSubtargetInfo.h"
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	116 #include <cassert>
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	117 #include <iterator>
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	118 #include <set>
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	119 #include <utility>
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	120
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	121 #define DEBUG_TYPE "expand-condsets"
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	122
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	123 using namespace llvm;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	124
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	125 static cl::opt<unsigned> OptTfrLimit("expand-condsets-tfr-limit",
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	126 cl::init(~0U), cl::Hidden, cl::desc("Max number of mux expansions"));
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	127 static cl::opt<unsigned> OptCoaLimit("expand-condsets-coa-limit",
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	128 cl::init(~0U), cl::Hidden, cl::desc("Max number of segment coalescings"));
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	129
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	130 namespace llvm {
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	131
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	132 void initializeHexagonExpandCondsetsPass(PassRegistry&);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	133 FunctionPass *createHexagonExpandCondsets();
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	134
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	135 } // end namespace llvm
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	136
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	137 namespace {
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	138
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	139 class HexagonExpandCondsets : public MachineFunctionPass {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	140 public:
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	141 static char ID;
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	142
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	143 HexagonExpandCondsets() : MachineFunctionPass(ID) {
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	144 if (OptCoaLimit.getPosition())
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	145 CoaLimitActive = true, CoaLimit = OptCoaLimit;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	146 if (OptTfrLimit.getPosition())
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	147 TfrLimitActive = true, TfrLimit = OptTfrLimit;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	148 initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	149 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	150
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	151 StringRef getPassName() const override { return "Hexagon Expand Condsets"; }
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	152
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	153 void getAnalysisUsage(AnalysisUsage &AU) const override {
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	154 AU.addRequired<LiveIntervals>();
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	155 AU.addPreserved<LiveIntervals>();
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	156 AU.addPreserved<SlotIndexes>();
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	157 AU.addRequired<MachineDominatorTree>();
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	158 AU.addPreserved<MachineDominatorTree>();
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	159 MachineFunctionPass::getAnalysisUsage(AU);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	160 }
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	161
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	162 bool runOnMachineFunction(MachineFunction &MF) override;
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	163
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	164 private:
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	165 const HexagonInstrInfo *HII = nullptr;
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	166 const TargetRegisterInfo *TRI = nullptr;
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	167 MachineDominatorTree *MDT;
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	168 MachineRegisterInfo *MRI = nullptr;
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	169 LiveIntervals *LIS = nullptr;
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	170 bool CoaLimitActive = false;
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	171 bool TfrLimitActive = false;
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	172 unsigned CoaLimit;
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	173 unsigned TfrLimit;
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	174 unsigned CoaCounter = 0;
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	175 unsigned TfrCounter = 0;
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	176
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	177 struct RegisterRef {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	178 RegisterRef(const MachineOperand &Op) : Reg(Op.getReg()),
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	179 Sub(Op.getSubReg()) {}
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	180 RegisterRef(unsigned R = 0, unsigned S = 0) : Reg(R), Sub(S) {}
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	181
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	182 bool operator== (RegisterRef RR) const {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	183 return Reg == RR.Reg && Sub == RR.Sub;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	184 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	185 bool operator!= (RegisterRef RR) const { return !operator==(RR); }
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	186 bool operator< (RegisterRef RR) const {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	187 return Reg < RR.Reg \|\| (Reg == RR.Reg && Sub < RR.Sub);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	188 }
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	189
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	190 unsigned Reg, Sub;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	191 };
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	192
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	193 using ReferenceMap = DenseMap<unsigned, unsigned>;
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	194 enum { Sub_Low = 0x1, Sub_High = 0x2, Sub_None = (Sub_Low \| Sub_High) };
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	195 enum { Exec_Then = 0x10, Exec_Else = 0x20 };
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	196
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	197 unsigned getMaskForSub(unsigned Sub);
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	198 bool isCondset(const MachineInstr &MI);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	199 LaneBitmask getLaneMask(unsigned Reg, unsigned Sub);
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	200
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	201 void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	202 bool isRefInMap(RegisterRef, ReferenceMap &Map, unsigned Exec);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	203
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	204 void updateDeadsInRange(unsigned Reg, LaneBitmask LM, LiveRange &Range);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	205 void updateKillFlags(unsigned Reg);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	206 void updateDeadFlags(unsigned Reg);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	207 void recalculateLiveInterval(unsigned Reg);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	208 void removeInstr(MachineInstr &MI);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	209 void updateLiveness(std::set<unsigned> &RegSet, bool Recalc,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	210 bool UpdateKills, bool UpdateDeads);
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	211
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	212 unsigned getCondTfrOpcode(const MachineOperand &SO, bool Cond);
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	213 MachineInstr *genCondTfrFor(MachineOperand &SrcOp,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	214 MachineBasicBlock::iterator At, unsigned DstR,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	215 unsigned DstSR, const MachineOperand &PredOp, bool PredSense,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	216 bool ReadUndef, bool ImpUse);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	217 bool split(MachineInstr &MI, std::set<unsigned> &UpdRegs);
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	218
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	219 bool isPredicable(MachineInstr *MI);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	220 MachineInstr *getReachingDefForPred(RegisterRef RD,
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	221 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond);
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	222 bool canMoveOver(MachineInstr &MI, ReferenceMap &Defs, ReferenceMap &Uses);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	223 bool canMoveMemTo(MachineInstr &MI, MachineInstr &ToI, bool IsDown);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	224 void predicateAt(const MachineOperand &DefOp, MachineInstr &MI,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	225 MachineBasicBlock::iterator Where,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	226 const MachineOperand &PredOp, bool Cond,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	227 std::set<unsigned> &UpdRegs);
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	228 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	229 bool Cond, MachineBasicBlock::iterator First,
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	230 MachineBasicBlock::iterator Last);
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	231 bool predicate(MachineInstr &TfrI, bool Cond, std::set<unsigned> &UpdRegs);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	232 bool predicateInBlock(MachineBasicBlock &B,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	233 std::set<unsigned> &UpdRegs);
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	234
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	235 bool isIntReg(RegisterRef RR, unsigned &BW);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	236 bool isIntraBlocks(LiveInterval &LI);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	237 bool coalesceRegisters(RegisterRef R1, RegisterRef R2);
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	238 bool coalesceSegments(const SmallVectorImpl<MachineInstr*> &Condsets,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	239 std::set<unsigned> &UpdRegs);
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	240 };
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	241
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	242 } // end anonymous namespace
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	243
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	244 char HexagonExpandCondsets::ID = 0;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	245
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	246 namespace llvm {
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	247
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	248 char &HexagonExpandCondsetsID = HexagonExpandCondsets::ID;
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	249
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	250 } // end namespace llvm
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	251
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	252 INITIALIZE_PASS_BEGIN(HexagonExpandCondsets, "expand-condsets",
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	253 "Hexagon Expand Condsets", false, false)
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	254 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	255 INITIALIZE_PASS_DEPENDENCY(SlotIndexes)
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	256 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	257 INITIALIZE_PASS_END(HexagonExpandCondsets, "expand-condsets",
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	258 "Hexagon Expand Condsets", false, false)
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	259
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	260 unsigned HexagonExpandCondsets::getMaskForSub(unsigned Sub) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	261 switch (Sub) {
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	262 case Hexagon::isub_lo:
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	263 case Hexagon::vsub_lo:
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	264 return Sub_Low;
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	265 case Hexagon::isub_hi:
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	266 case Hexagon::vsub_hi:
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	267 return Sub_High;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	268 case Hexagon::NoSubRegister:
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	269 return Sub_None;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	270 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	271 llvm_unreachable("Invalid subregister");
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	272 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	273
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	274 bool HexagonExpandCondsets::isCondset(const MachineInstr &MI) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	275 unsigned Opc = MI.getOpcode();
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	276 switch (Opc) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	277 case Hexagon::C2_mux:
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	278 case Hexagon::C2_muxii:
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	279 case Hexagon::C2_muxir:
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	280 case Hexagon::C2_muxri:
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	281 case Hexagon::PS_pselect:
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	282 return true;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	283 break;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	284 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	285 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	286 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	287
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	288 LaneBitmask HexagonExpandCondsets::getLaneMask(unsigned Reg, unsigned Sub) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	289 assert(TargetRegisterInfo::isVirtualRegister(Reg));
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	290 return Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	291 : MRI->getMaxLaneMaskForVReg(Reg);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	292 }
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	293
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	294 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map,
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	295 unsigned Exec) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	296 unsigned Mask = getMaskForSub(RR.Sub) \| Exec;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	297 ReferenceMap::iterator F = Map.find(RR.Reg);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	298 if (F == Map.end())
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	299 Map.insert(std::make_pair(RR.Reg, Mask));
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	300 else
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	301 F->second \|= Mask;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	302 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	303
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	304 bool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map,
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	305 unsigned Exec) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	306 ReferenceMap::iterator F = Map.find(RR.Reg);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	307 if (F == Map.end())
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	308 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	309 unsigned Mask = getMaskForSub(RR.Sub) \| Exec;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	310 if (Mask & F->second)
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	311 return true;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	312 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	313 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	314
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	315 void HexagonExpandCondsets::updateKillFlags(unsigned Reg) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	316 auto KillAt = [this,Reg] (SlotIndex K, LaneBitmask LM) -> void {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	317 // Set the <kill> flag on a use of Reg whose lane mask is contained in LM.
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	318 MachineInstr *MI = LIS->getInstructionFromIndex(K);
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	319 for (auto &Op : MI->operands()) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	320 if (!Op.isReg() \|\| !Op.isUse() \|\| Op.getReg() != Reg)
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	321 continue;
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	322 LaneBitmask SLM = getLaneMask(Reg, Op.getSubReg());
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	323 if ((SLM & LM) == SLM) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	324 // Only set the kill flag on the first encountered use of Reg in this
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	325 // instruction.
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	326 Op.setIsKill(true);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	327 break;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	328 }
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	329 }
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	330 };
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	331
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	332 LiveInterval &LI = LIS->getInterval(Reg);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	333 for (auto I = LI.begin(), E = LI.end(); I != E; ++I) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	334 if (!I->end.isRegister())
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	335 continue;
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	336 // Do not mark the end of the segment as <kill>, if the next segment
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	337 // starts with a predicated instruction.
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	338 auto NextI = std::next(I);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	339 if (NextI != E && NextI->start.isRegister()) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	340 MachineInstr *DefI = LIS->getInstructionFromIndex(NextI->start);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	341 if (HII->isPredicated(*DefI))
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	342 continue;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	343 }
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	344 bool WholeReg = true;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	345 if (LI.hasSubRanges()) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	346 auto EndsAtI = [I] (LiveInterval::SubRange &S) -> bool {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	347 LiveRange::iterator F = S.find(I->end);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	348 return F != S.end() && I->end == F->end;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	349 };
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	350 // Check if all subranges end at I->end. If so, make sure to kill
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	351 // the whole register.
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	352 for (LiveInterval::SubRange &S : LI.subranges()) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	353 if (EndsAtI(S))
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	354 KillAt(I->end, S.LaneMask);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	355 else
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	356 WholeReg = false;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	357 }
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	358 }
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	359 if (WholeReg)
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	360 KillAt(I->end, MRI->getMaxLaneMaskForVReg(Reg));
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	361 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	362 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	363
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	364 void HexagonExpandCondsets::updateDeadsInRange(unsigned Reg, LaneBitmask LM,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	365 LiveRange &Range) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	366 assert(TargetRegisterInfo::isVirtualRegister(Reg));
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	367 if (Range.empty())
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	368 return;
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	369
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	370 // Return two booleans: { def-modifes-reg, def-covers-reg }.
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	371 auto IsRegDef = [this,Reg,LM] (MachineOperand &Op) -> std::pair<bool,bool> {
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	372 if (!Op.isReg() \|\| !Op.isDef())
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	373 return { false, false };
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	374 unsigned DR = Op.getReg(), DSR = Op.getSubReg();
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	375 if (!TargetRegisterInfo::isVirtualRegister(DR) \|\| DR != Reg)
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	376 return { false, false };
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	377 LaneBitmask SLM = getLaneMask(DR, DSR);
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	378 LaneBitmask A = SLM & LM;
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	379 return { A.any(), A == SLM };
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	380 };
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	381
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	382 // The splitting step will create pairs of predicated definitions without
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	383 // any implicit uses (since implicit uses would interfere with predication).
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	384 // This can cause the reaching defs to become dead after live range
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	385 // recomputation, even though they are not really dead.
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	386 // We need to identify predicated defs that need implicit uses, and
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	387 // dead defs that are not really dead, and correct both problems.
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	388
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	389 auto Dominate = [this] (SetVector<MachineBasicBlock*> &Defs,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	390 MachineBasicBlock *Dest) -> bool {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	391 for (MachineBasicBlock *D : Defs)
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	392 if (D != Dest && MDT->dominates(D, Dest))
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	393 return true;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	394
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	395 MachineBasicBlock *Entry = &Dest->getParent()->front();
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	396 SetVector<MachineBasicBlock*> Work(Dest->pred_begin(), Dest->pred_end());
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	397 for (unsigned i = 0; i < Work.size(); ++i) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	398 MachineBasicBlock *B = Work[i];
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	399 if (Defs.count(B))
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	400 continue;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	401 if (B == Entry)
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	402 return false;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	403 for (auto *P : B->predecessors())
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	404 Work.insert(P);
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	405 }
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	406 return true;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	407 };
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	408
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	409 // First, try to extend live range within individual basic blocks. This
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	410 // will leave us only with dead defs that do not reach any predicated
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	411 // defs in the same block.
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	412 SetVector<MachineBasicBlock*> Defs;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	413 SmallVector<SlotIndex,4> PredDefs;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	414 for (auto &Seg : Range) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	415 if (!Seg.start.isRegister())
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	416 continue;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	417 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	418 Defs.insert(DefI->getParent());
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	419 if (HII->isPredicated(*DefI))
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	420 PredDefs.push_back(Seg.start);
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	421 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	422
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	423 SmallVector<SlotIndex,8> Undefs;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	424 LiveInterval &LI = LIS->getInterval(Reg);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	425 LI.computeSubRangeUndefs(Undefs, LM, MRI, LIS->getSlotIndexes());
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	426
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	427 for (auto &SI : PredDefs) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	428 MachineBasicBlock *BB = LIS->getMBBFromIndex(SI);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	429 auto P = Range.extendInBlock(Undefs, LIS->getMBBStartIdx(BB), SI);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	430 if (P.first != nullptr \|\| P.second)
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	431 SI = SlotIndex();
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	432 }
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	433
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	434 // Calculate reachability for those predicated defs that were not handled
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	435 // by the in-block extension.
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	436 SmallVector<SlotIndex,4> ExtTo;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	437 for (auto &SI : PredDefs) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	438 if (!SI.isValid())
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	439 continue;
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	440 MachineBasicBlock *BB = LIS->getMBBFromIndex(SI);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	441 if (BB->pred_empty())
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	442 continue;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	443 // If the defs from this range reach SI via all predecessors, it is live.
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	444 // It can happen that SI is reached by the defs through some paths, but
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	445 // not all. In the IR coming into this optimization, SI would not be
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	446 // considered live, since the defs would then not jointly dominate SI.
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	447 // That means that SI is an overwriting def, and no implicit use is
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	448 // needed at this point. Do not add SI to the extension points, since
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	449 // extendToIndices will abort if there is no joint dominance.
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	450 // If the abort was avoided by adding extra undefs added to Undefs,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	451 // extendToIndices could actually indicate that SI is live, contrary
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	452 // to the original IR.
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	453 if (Dominate(Defs, BB))
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	454 ExtTo.push_back(SI);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	455 }
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	456
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	457 if (!ExtTo.empty())
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	458 LIS->extendToIndices(Range, ExtTo, Undefs);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	459
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	460 // Remove <dead> flags from all defs that are not dead after live range
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	461 // extension, and collect all def operands. They will be used to generate
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	462 // the necessary implicit uses.
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	463 // At the same time, add <dead> flag to all defs that are actually dead.
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	464 // This can happen, for example, when a mux with identical inputs is
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	465 // replaced with a COPY: the use of the predicate register disappears and
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	466 // the dead can become dead.
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	467 std::set<RegisterRef> DefRegs;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	468 for (auto &Seg : Range) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	469 if (!Seg.start.isRegister())
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	470 continue;
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	471 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	472 for (auto &Op : DefI->operands()) {
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	473 auto P = IsRegDef(Op);
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	474 if (P.second && Seg.end.isDead()) {
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	475 Op.setIsDead(true);
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	476 } else if (P.first) {
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	477 DefRegs.insert(Op);
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	478 Op.setIsDead(false);
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	479 }
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	480 }
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	481 }
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	482
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	483 // Now, add implicit uses to each predicated def that is reached
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	484 // by other defs.
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	485 for (auto &Seg : Range) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	486 if (!Seg.start.isRegister() \|\| !Range.liveAt(Seg.start.getPrevSlot()))
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	487 continue;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	488 MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	489 if (!HII->isPredicated(*DefI))
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	490 continue;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	491 // Construct the set of all necessary implicit uses, based on the def
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	492 // operands in the instruction. We need to tie the implicit uses to
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	493 // the corresponding defs.
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	494 std::map<RegisterRef,unsigned> ImpUses;
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	495 for (unsigned i = 0, e = DefI->getNumOperands(); i != e; ++i) {
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	496 MachineOperand &Op = DefI->getOperand(i);
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	497 if (!Op.isReg() \|\| !DefRegs.count(Op))
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	498 continue;
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	499 if (Op.isDef()) {
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	500 ImpUses.insert({Op, i});
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	501 } else {
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	502 // This function can be called for the same register with different
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	503 // lane masks. If the def in this instruction was for the whole
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	504 // register, we can get here more than once. Avoid adding multiple
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	505 // implicit uses (or adding an implicit use when an explicit one is
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	506 // present).
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	507 ImpUses.erase(Op);
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	508 }
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	509 }
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	510 if (ImpUses.empty())
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	511 continue;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	512 MachineFunction &MF = *DefI->getParent()->getParent();
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	513 for (std::pair<RegisterRef, unsigned> P : ImpUses) {
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	514 RegisterRef R = P.first;
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	515 MachineInstrBuilder(MF, DefI).addReg(R.Reg, RegState::Implicit, R.Sub);
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	516 DefI->tieOperands(P.second, DefI->getNumOperands()-1);
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	517 }
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	518 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	519 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	520
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	521 void HexagonExpandCondsets::updateDeadFlags(unsigned Reg) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	522 LiveInterval &LI = LIS->getInterval(Reg);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	523 if (LI.hasSubRanges()) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	524 for (LiveInterval::SubRange &S : LI.subranges()) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	525 updateDeadsInRange(Reg, S.LaneMask, S);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	526 LIS->shrinkToUses(S, Reg);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	527 }
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	528 LI.clear();
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	529 LIS->constructMainRangeFromSubranges(LI);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	530 } else {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	531 updateDeadsInRange(Reg, MRI->getMaxLaneMaskForVReg(Reg), LI);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	532 }
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	533 }
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	534
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	535 void HexagonExpandCondsets::recalculateLiveInterval(unsigned Reg) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	536 LIS->removeInterval(Reg);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	537 LIS->createAndComputeVirtRegInterval(Reg);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	538 }
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	539
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	540 void HexagonExpandCondsets::removeInstr(MachineInstr &MI) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	541 LIS->RemoveMachineInstrFromMaps(MI);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	542 MI.eraseFromParent();
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	543 }
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	544
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	545 void HexagonExpandCondsets::updateLiveness(std::set<unsigned> &RegSet,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	546 bool Recalc, bool UpdateKills, bool UpdateDeads) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	547 UpdateKills \|= UpdateDeads;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	548 for (auto R : RegSet) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	549 if (Recalc)
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	550 recalculateLiveInterval(R);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	551 if (UpdateKills)
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	552 MRI->clearKillFlags(R);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	553 if (UpdateDeads)
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	554 updateDeadFlags(R);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	555 // Fixing <dead> flags may extend live ranges, so reset <kill> flags
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	556 // after that.
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	557 if (UpdateKills)
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	558 updateKillFlags(R);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	559 LIS->getInterval(R).verify();
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	560 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	561 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	562
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	563 /// Get the opcode for a conditional transfer of the value in SO (source
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	564 /// operand). The condition (true/false) is given in Cond.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	565 unsigned HexagonExpandCondsets::getCondTfrOpcode(const MachineOperand &SO,
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	566 bool IfTrue) {
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	567 using namespace Hexagon;
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	568
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	569 if (SO.isReg()) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	570 unsigned PhysR;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	571 RegisterRef RS = SO;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	572 if (TargetRegisterInfo::isVirtualRegister(RS.Reg)) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	573 const TargetRegisterClass *VC = MRI->getRegClass(RS.Reg);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	574 assert(VC->begin() != VC->end() && "Empty register class");
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	575 PhysR = *VC->begin();
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	576 } else {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	577 assert(TargetRegisterInfo::isPhysicalRegister(RS.Reg));
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	578 PhysR = RS.Reg;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	579 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	580 unsigned PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	581 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS);
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	582 switch (TRI->getRegSizeInBits(*RC)) {
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	583 case 32:
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	584 return IfTrue ? A2_tfrt : A2_tfrf;
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	585 case 64:
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	586 return IfTrue ? A2_tfrpt : A2_tfrpf;
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	587 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	588 llvm_unreachable("Invalid register operand");
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	589 }
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	590 switch (SO.getType()) {
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	591 case MachineOperand::MO_Immediate:
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	592 case MachineOperand::MO_FPImmediate:
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	593 case MachineOperand::MO_ConstantPoolIndex:
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	594 case MachineOperand::MO_TargetIndex:
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	595 case MachineOperand::MO_JumpTableIndex:
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	596 case MachineOperand::MO_ExternalSymbol:
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	597 case MachineOperand::MO_GlobalAddress:
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	598 case MachineOperand::MO_BlockAddress:
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	599 return IfTrue ? C2_cmoveit : C2_cmoveif;
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	600 default:
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	601 break;
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	602 }
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	603 llvm_unreachable("Unexpected source operand");
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	604 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	605
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	606 /// Generate a conditional transfer, copying the value SrcOp to the
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	607 /// destination register DstR:DstSR, and using the predicate register from
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	608 /// PredOp. The Cond argument specifies whether the predicate is to be
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	609 /// if(PredOp), or if(!PredOp).
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	610 MachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	611 MachineBasicBlock::iterator At,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	612 unsigned DstR, unsigned DstSR, const MachineOperand &PredOp,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	613 bool PredSense, bool ReadUndef, bool ImpUse) {
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	614 MachineInstr *MI = SrcOp.getParent();
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	615 MachineBasicBlock &B = *At->getParent();
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	616 const DebugLoc &DL = MI->getDebugLoc();
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	617
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	618 // Don't avoid identity copies here (i.e. if the source and the destination
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	619 // are the same registers). It is actually better to generate them here,
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	620 // since this would cause the copy to potentially be predicated in the next
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	621 // step. The predication will remove such a copy if it is unable to
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	622 /// predicate.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	623
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	624 unsigned Opc = getCondTfrOpcode(SrcOp, PredSense);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	625 unsigned DstState = RegState::Define \| (ReadUndef ? RegState::Undef : 0);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	626 unsigned PredState = getRegState(PredOp) & ~RegState::Kill;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	627 MachineInstrBuilder MIB;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	628
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	629 if (SrcOp.isReg()) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	630 unsigned SrcState = getRegState(SrcOp);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	631 if (RegisterRef(SrcOp) == RegisterRef(DstR, DstSR))
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	632 SrcState &= ~RegState::Kill;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	633 MIB = BuildMI(B, At, DL, HII->get(Opc))
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	634 .addReg(DstR, DstState, DstSR)
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	635 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	636 .addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg());
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	637 } else {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	638 MIB = BuildMI(B, At, DL, HII->get(Opc))
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	639 .addReg(DstR, DstState, DstSR)
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	640 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	641 .add(SrcOp);
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	642 }
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	643
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	644 DEBUG(dbgs() << "created an initial copy: " << *MIB);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	645 return &*MIB;
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	646 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	647
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	648 /// Replace a MUX instruction MI with a pair A2_tfrt/A2_tfrf. This function
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	649 /// performs all necessary changes to complete the replacement.
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	650 bool HexagonExpandCondsets::split(MachineInstr &MI,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	651 std::set<unsigned> &UpdRegs) {
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	652 if (TfrLimitActive) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	653 if (TfrCounter >= TfrLimit)
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	654 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	655 TfrCounter++;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	656 }
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	657 DEBUG(dbgs() << "\nsplitting BB#" << MI.getParent()->getNumber() << ": "
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	658 << MI);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	659 MachineOperand &MD = MI.getOperand(0); // Definition
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	660 MachineOperand &MP = MI.getOperand(1); // Predicate register
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	661 assert(MD.isDef());
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	662 unsigned DR = MD.getReg(), DSR = MD.getSubReg();
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	663 bool ReadUndef = MD.isUndef();
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	664 MachineBasicBlock::iterator At = MI;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	665
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	666 auto updateRegs = [&UpdRegs] (const MachineInstr &MI) -> void {
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	667 for (auto &Op : MI.operands())
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	668 if (Op.isReg())
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	669 UpdRegs.insert(Op.getReg());
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	670 };
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	671
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	672 // If this is a mux of the same register, just replace it with COPY.
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	673 // Ideally, this would happen earlier, so that register coalescing would
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	674 // see it.
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	675 MachineOperand &ST = MI.getOperand(2);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	676 MachineOperand &SF = MI.getOperand(3);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	677 if (ST.isReg() && SF.isReg()) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	678 RegisterRef RT(ST);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	679 if (RT == RegisterRef(SF)) {
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	680 // Copy regs to update first.
803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	681 updateRegs(MI);
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	682 MI.setDesc(HII->get(TargetOpcode::COPY));
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	683 unsigned S = getRegState(ST);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	684 while (MI.getNumOperands() > 1)
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	685 MI.RemoveOperand(MI.getNumOperands()-1);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	686 MachineFunction &MF = *MI.getParent()->getParent();
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	687 MachineInstrBuilder(MF, MI).addReg(RT.Reg, S, RT.Sub);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	688 return true;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	689 }
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	690 }
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	691
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	692 // First, create the two invididual conditional transfers, and add each
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	693 // of them to the live intervals information. Do that first and then remove
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	694 // the old instruction from live intervals.
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	695 MachineInstr *TfrT =
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	696 genCondTfrFor(ST, At, DR, DSR, MP, true, ReadUndef, false);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	697 MachineInstr *TfrF =
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	698 genCondTfrFor(SF, At, DR, DSR, MP, false, ReadUndef, true);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	699 LIS->InsertMachineInstrInMaps(*TfrT);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	700 LIS->InsertMachineInstrInMaps(*TfrF);
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	701
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	702 // Will need to recalculate live intervals for all registers in MI.
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	703 updateRegs(MI);
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	704
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	705 removeInstr(MI);
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	706 return true;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	707 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	708
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	709 bool HexagonExpandCondsets::isPredicable(MachineInstr *MI) {
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	710 if (HII->isPredicated(MI) \|\| !HII->isPredicable(MI))
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	711 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	712 if (MI->hasUnmodeledSideEffects() \|\| MI->mayStore())
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	713 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	714 // Reject instructions with multiple defs (e.g. post-increment loads).
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	715 bool HasDef = false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	716 for (auto &Op : MI->operands()) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	717 if (!Op.isReg() \|\| !Op.isDef())
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	718 continue;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	719 if (HasDef)
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	720 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	721 HasDef = true;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	722 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	723 for (auto &Mo : MI->memoperands())
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	724 if (Mo->isVolatile())
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	725 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	726 return true;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	727 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	728
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	729 /// Find the reaching definition for a predicated use of RD. The RD is used
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	730 /// under the conditions given by PredR and Cond, and this function will ignore
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	731 /// definitions that set RD under the opposite conditions.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	732 MachineInstr *HexagonExpandCondsets::getReachingDefForPred(RegisterRef RD,
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	733 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	734 MachineBasicBlock &B = *UseIt->getParent();
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	735 MachineBasicBlock::iterator I = UseIt, S = B.begin();
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	736 if (I == S)
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	737 return nullptr;
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	738
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	739 bool PredValid = true;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	740 do {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	741 --I;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	742 MachineInstr MI = &I;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	743 // Check if this instruction can be ignored, i.e. if it is predicated
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	744 // on the complementary condition.
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	745 if (PredValid && HII->isPredicated(*MI)) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	746 if (MI->readsRegister(PredR) && (Cond != HII->isPredicatedTrue(*MI)))
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	747 continue;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	748 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	749
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	750 // Check the defs. If the PredR is defined, invalidate it. If RD is
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	751 // defined, return the instruction or 0, depending on the circumstances.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	752 for (auto &Op : MI->operands()) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	753 if (!Op.isReg() \|\| !Op.isDef())
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	754 continue;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	755 RegisterRef RR = Op;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	756 if (RR.Reg == PredR) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	757 PredValid = false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	758 continue;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	759 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	760 if (RR.Reg != RD.Reg)
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	761 continue;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	762 // If the "Reg" part agrees, there is still the subregister to check.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	763 // If we are looking for vreg1:loreg, we can skip vreg1:hireg, but
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	764 // not vreg1 (w/o subregisters).
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	765 if (RR.Sub == RD.Sub)
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	766 return MI;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	767 if (RR.Sub == 0 \|\| RD.Sub == 0)
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	768 return nullptr;
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	769 // We have different subregisters, so we can continue looking.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	770 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	771 } while (I != S);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	772
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	773 return nullptr;
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	774 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	775
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	776 /// Check if the instruction MI can be safely moved over a set of instructions
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	777 /// whose side-effects (in terms of register defs and uses) are expressed in
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	778 /// the maps Defs and Uses. These maps reflect the conditional defs and uses
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	779 /// that depend on the same predicate register to allow moving instructions
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	780 /// over instructions predicated on the opposite condition.
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	781 bool HexagonExpandCondsets::canMoveOver(MachineInstr &MI, ReferenceMap &Defs,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	782 ReferenceMap &Uses) {
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	783 // In order to be able to safely move MI over instructions that define
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	784 // "Defs" and use "Uses", no def operand from MI can be defined or used
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	785 // and no use operand can be defined.
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	786 for (auto &Op : MI.operands()) {
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	787 if (!Op.isReg())
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	788 continue;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	789 RegisterRef RR = Op;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	790 // For physical register we would need to check register aliases, etc.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	791 // and we don't want to bother with that. It would be of little value
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	792 // before the actual register rewriting (from virtual to physical).
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	793 if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	794 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	795 // No redefs for any operand.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	796 if (isRefInMap(RR, Defs, Exec_Then))
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	797 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	798 // For defs, there cannot be uses.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	799 if (Op.isDef() && isRefInMap(RR, Uses, Exec_Then))
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	800 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	801 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	802 return true;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	803 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	804
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	805 /// Check if the instruction accessing memory (TheI) can be moved to the
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	806 /// location ToI.
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	807 bool HexagonExpandCondsets::canMoveMemTo(MachineInstr &TheI, MachineInstr &ToI,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	808 bool IsDown) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	809 bool IsLoad = TheI.mayLoad(), IsStore = TheI.mayStore();
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	810 if (!IsLoad && !IsStore)
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	811 return true;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	812 if (HII->areMemAccessesTriviallyDisjoint(TheI, ToI))
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	813 return true;
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	814 if (TheI.hasUnmodeledSideEffects())
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	815 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	816
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	817 MachineBasicBlock::iterator StartI = IsDown ? TheI : ToI;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	818 MachineBasicBlock::iterator EndI = IsDown ? ToI : TheI;
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	819 bool Ordered = TheI.hasOrderedMemoryRef();
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	820
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	821 // Search for aliased memory reference in (StartI, EndI).
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	822 for (MachineBasicBlock::iterator I = std::next(StartI); I != EndI; ++I) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	823 MachineInstr MI = &I;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	824 if (MI->hasUnmodeledSideEffects())
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	825 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	826 bool L = MI->mayLoad(), S = MI->mayStore();
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	827 if (!L && !S)
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	828 continue;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	829 if (Ordered && MI->hasOrderedMemoryRef())
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	830 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	831
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	832 bool Conflict = (L && IsStore) \|\| S;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	833 if (Conflict)
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	834 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	835 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	836 return true;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	837 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	838
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	839 /// Generate a predicated version of MI (where the condition is given via
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	840 /// PredR and Cond) at the point indicated by Where.
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	841 void HexagonExpandCondsets::predicateAt(const MachineOperand &DefOp,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	842 MachineInstr &MI,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	843 MachineBasicBlock::iterator Where,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	844 const MachineOperand &PredOp, bool Cond,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	845 std::set<unsigned> &UpdRegs) {
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	846 // The problem with updating live intervals is that we can move one def
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	847 // past another def. In particular, this can happen when moving an A2_tfrt
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	848 // over an A2_tfrf defining the same register. From the point of view of
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	849 // live intervals, these two instructions are two separate definitions,
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	850 // and each one starts another live segment. LiveIntervals's "handleMove"
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	851 // does not allow such moves, so we need to handle it ourselves. To avoid
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	852 // invalidating liveness data while we are using it, the move will be
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	853 // implemented in 4 steps: (1) add a clone of the instruction MI at the
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	854 // target location, (2) update liveness, (3) delete the old instruction,
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	855 // and (4) update liveness again.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	856
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	857 MachineBasicBlock &B = *MI.getParent();
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	858 DebugLoc DL = Where->getDebugLoc(); // "Where" points to an instruction.
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	859 unsigned Opc = MI.getOpcode();
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	860 unsigned PredOpc = HII->getCondOpcode(Opc, !Cond);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	861 MachineInstrBuilder MB = BuildMI(B, Where, DL, HII->get(PredOpc));
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	862 unsigned Ox = 0, NP = MI.getNumOperands();
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	863 // Skip all defs from MI first.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	864 while (Ox < NP) {
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	865 MachineOperand &MO = MI.getOperand(Ox);
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	866 if (!MO.isReg() \|\| !MO.isDef())
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	867 break;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	868 Ox++;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	869 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	870 // Add the new def, then the predicate register, then the rest of the
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	871 // operands.
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	872 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg());
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	873 MB.addReg(PredOp.getReg(), PredOp.isUndef() ? RegState::Undef : 0,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	874 PredOp.getSubReg());
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	875 while (Ox < NP) {
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	876 MachineOperand &MO = MI.getOperand(Ox);
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	877 if (!MO.isReg() \|\| !MO.isImplicit())
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	878 MB.add(MO);
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	879 Ox++;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	880 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	881
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	882 MachineFunction &MF = *B.getParent();
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	883 MachineInstr::mmo_iterator I = MI.memoperands_begin();
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	884 unsigned NR = std::distance(I, MI.memoperands_end());
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	885 MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(NR);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	886 for (unsigned i = 0; i < NR; ++i)
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	887 MemRefs[i] = *I++;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	888 MB.setMemRefs(MemRefs, MemRefs+NR);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	889
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	890 MachineInstr *NewI = MB;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	891 NewI->clearKillInfo();
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	892 LIS->InsertMachineInstrInMaps(*NewI);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	893
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	894 for (auto &Op : NewI->operands())
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	895 if (Op.isReg())
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	896 UpdRegs.insert(Op.getReg());
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	897 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	898
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	899 /// In the range [First, Last], rename all references to the "old" register RO
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	900 /// to the "new" register RN, but only in instructions predicated on the given
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	901 /// condition.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	902 void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN,
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	903 unsigned PredR, bool Cond, MachineBasicBlock::iterator First,
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	904 MachineBasicBlock::iterator Last) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	905 MachineBasicBlock::iterator End = std::next(Last);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	906 for (MachineBasicBlock::iterator I = First; I != End; ++I) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	907 MachineInstr MI = &I;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	908 // Do not touch instructions that are not predicated, or are predicated
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	909 // on the opposite condition.
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	910 if (!HII->isPredicated(*MI))
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	911 continue;
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	912 if (!MI->readsRegister(PredR) \|\| (Cond != HII->isPredicatedTrue(*MI)))
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	913 continue;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	914
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	915 for (auto &Op : MI->operands()) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	916 if (!Op.isReg() \|\| RO != RegisterRef(Op))
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	917 continue;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	918 Op.setReg(RN.Reg);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	919 Op.setSubReg(RN.Sub);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	920 // In practice, this isn't supposed to see any defs.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	921 assert(!Op.isDef() && "Not expecting a def");
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	922 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	923 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	924 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	925
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	926 /// For a given conditional copy, predicate the definition of the source of
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	927 /// the copy under the given condition (using the same predicate register as
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	928 /// the copy).
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	929 bool HexagonExpandCondsets::predicate(MachineInstr &TfrI, bool Cond,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	930 std::set<unsigned> &UpdRegs) {
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	931 // TfrI - A2_tfr[tf] Instruction (not A2_tfrsi).
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	932 unsigned Opc = TfrI.getOpcode();
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	933 (void)Opc;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	934 assert(Opc == Hexagon::A2_tfrt \|\| Opc == Hexagon::A2_tfrf);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	935 DEBUG(dbgs() << "\nattempt to predicate if-" << (Cond ? "true" : "false")
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	936 << ": " << TfrI);
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	937
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	938 MachineOperand &MD = TfrI.getOperand(0);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	939 MachineOperand &MP = TfrI.getOperand(1);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	940 MachineOperand &MS = TfrI.getOperand(2);
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	941 // The source operand should be a <kill>. This is not strictly necessary,
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	942 // but it makes things a lot simpler. Otherwise, we would need to rename
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	943 // some registers, which would complicate the transformation considerably.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	944 if (!MS.isKill())
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	945 return false;
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	946 // Avoid predicating instructions that define a subregister if subregister
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	947 // liveness tracking is not enabled.
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	948 if (MD.getSubReg() && !MRI->shouldTrackSubRegLiveness(MD.getReg()))
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	949 return false;
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	950
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	951 RegisterRef RT(MS);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	952 unsigned PredR = MP.getReg();
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	953 MachineInstr *DefI = getReachingDefForPred(RT, TfrI, PredR, Cond);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	954 if (!DefI \|\| !isPredicable(DefI))
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	955 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	956
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	957 DEBUG(dbgs() << "Source def: " << *DefI);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	958
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	959 // Collect the information about registers defined and used between the
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	960 // DefI and the TfrI.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	961 // Map: reg -> bitmask of subregs
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	962 ReferenceMap Uses, Defs;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	963 MachineBasicBlock::iterator DefIt = DefI, TfrIt = TfrI;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	964
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	965 // Check if the predicate register is valid between DefI and TfrI.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	966 // If it is, we can then ignore instructions predicated on the negated
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	967 // conditions when collecting def and use information.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	968 bool PredValid = true;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	969 for (MachineBasicBlock::iterator I = std::next(DefIt); I != TfrIt; ++I) {
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	970 if (!I->modifiesRegister(PredR, nullptr))
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	971 continue;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	972 PredValid = false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	973 break;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	974 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	975
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	976 for (MachineBasicBlock::iterator I = std::next(DefIt); I != TfrIt; ++I) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	977 MachineInstr MI = &I;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	978 // If this instruction is predicated on the same register, it could
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	979 // potentially be ignored.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	980 // By default assume that the instruction executes on the same condition
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	981 // as TfrI (Exec_Then), and also on the opposite one (Exec_Else).
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	982 unsigned Exec = Exec_Then \| Exec_Else;
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	983 if (PredValid && HII->isPredicated(*MI) && MI->readsRegister(PredR))
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	984 Exec = (Cond == HII->isPredicatedTrue(*MI)) ? Exec_Then : Exec_Else;
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	985
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	986 for (auto &Op : MI->operands()) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	987 if (!Op.isReg())
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	988 continue;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	989 // We don't want to deal with physical registers. The reason is that
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	990 // they can be aliased with other physical registers. Aliased virtual
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	991 // registers must share the same register number, and can only differ
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	992 // in the subregisters, which we are keeping track of. Physical
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	993 // registers ters no longer have subregisters---their super- and
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	994 // subregisters are other physical registers, and we are not checking
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	995 // that.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	996 RegisterRef RR = Op;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	997 if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	998 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	999
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1000 ReferenceMap &Map = Op.isDef() ? Defs : Uses;
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1001 if (Op.isDef() && Op.isUndef()) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1002 assert(RR.Sub && "Expecting a subregister on <def,read-undef>");
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1003 // If this is a <def,read-undef>, then it invalidates the non-written
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1004 // part of the register. For the purpose of checking the validity of
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1005 // the move, assume that it modifies the whole register.
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1006 RR.Sub = 0;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1007 }
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1008 addRefToMap(RR, Map, Exec);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1009 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1010 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1011
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1012 // The situation:
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1013 // RT = DefI
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1014 // ...
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1015 // RD = TfrI ..., RT
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1016
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1017 // If the register-in-the-middle (RT) is used or redefined between
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1018 // DefI and TfrI, we may not be able proceed with this transformation.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1019 // We can ignore a def that will not execute together with TfrI, and a
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1020 // use that will. If there is such a use (that does execute together with
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1021 // TfrI), we will not be able to move DefI down. If there is a use that
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1022 // executed if TfrI's condition is false, then RT must be available
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1023 // unconditionally (cannot be predicated).
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1024 // Essentially, we need to be able to rename RT to RD in this segment.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1025 if (isRefInMap(RT, Defs, Exec_Then) \|\| isRefInMap(RT, Uses, Exec_Else))
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1026 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1027 RegisterRef RD = MD;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1028 // If the predicate register is defined between DefI and TfrI, the only
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1029 // potential thing to do would be to move the DefI down to TfrI, and then
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1030 // predicate. The reaching def (DefI) must be movable down to the location
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1031 // of the TfrI.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1032 // If the target register of the TfrI (RD) is not used or defined between
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1033 // DefI and TfrI, consider moving TfrI up to DefI.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1034 bool CanUp = canMoveOver(TfrI, Defs, Uses);
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1035 bool CanDown = canMoveOver(*DefI, Defs, Uses);
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1036 // The TfrI does not access memory, but DefI could. Check if it's safe
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1037 // to move DefI down to TfrI.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1038 if (DefI->mayLoad() \|\| DefI->mayStore())
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1039 if (!canMoveMemTo(*DefI, TfrI, true))
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1040 CanDown = false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1041
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1042 DEBUG(dbgs() << "Can move up: " << (CanUp ? "yes" : "no")
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1043 << ", can move down: " << (CanDown ? "yes\n" : "no\n"));
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1044 MachineBasicBlock::iterator PastDefIt = std::next(DefIt);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1045 if (CanUp)
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1046 predicateAt(MD, *DefI, PastDefIt, MP, Cond, UpdRegs);
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1047 else if (CanDown)
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1048 predicateAt(MD, *DefI, TfrIt, MP, Cond, UpdRegs);
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1049 else
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1050 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1051
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1052 if (RT != RD) {
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1053 renameInRange(RT, RD, PredR, Cond, PastDefIt, TfrIt);
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1054 UpdRegs.insert(RT.Reg);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1055 }
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1056
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1057 removeInstr(TfrI);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1058 removeInstr(*DefI);
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1059 return true;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1060 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1061
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1062 /// Predicate all cases of conditional copies in the specified block.
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1063 bool HexagonExpandCondsets::predicateInBlock(MachineBasicBlock &B,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1064 std::set<unsigned> &UpdRegs) {
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1065 bool Changed = false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1066 MachineBasicBlock::iterator I, E, NextI;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1067 for (I = B.begin(), E = B.end(); I != E; I = NextI) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1068 NextI = std::next(I);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1069 unsigned Opc = I->getOpcode();
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1070 if (Opc == Hexagon::A2_tfrt \|\| Opc == Hexagon::A2_tfrf) {
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1071 bool Done = predicate(*I, (Opc == Hexagon::A2_tfrt), UpdRegs);
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1072 if (!Done) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1073 // If we didn't predicate I, we may need to remove it in case it is
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1074 // an "identity" copy, e.g. vreg1 = A2_tfrt vreg2, vreg1.
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1075 if (RegisterRef(I->getOperand(0)) == RegisterRef(I->getOperand(2))) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1076 for (auto &Op : I->operands())
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1077 if (Op.isReg())
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1078 UpdRegs.insert(Op.getReg());
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1079 removeInstr(*I);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1080 }
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1081 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1082 Changed \|= Done;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1083 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1084 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1085 return Changed;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1086 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1087
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1088 bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1089 if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1090 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1091 const TargetRegisterClass *RC = MRI->getRegClass(RR.Reg);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1092 if (RC == &Hexagon::IntRegsRegClass) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1093 BW = 32;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1094 return true;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1095 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1096 if (RC == &Hexagon::DoubleRegsRegClass) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1097 BW = (RR.Sub != 0) ? 32 : 64;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1098 return true;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1099 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1100 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1101 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1102
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1103 bool HexagonExpandCondsets::isIntraBlocks(LiveInterval &LI) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1104 for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1105 LiveRange::Segment &LR = *I;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1106 // Range must start at a register...
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1107 if (!LR.start.isRegister())
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1108 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1109 // ...and end in a register or in a dead slot.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1110 if (!LR.end.isRegister() && !LR.end.isDead())
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1111 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1112 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1113 return true;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1114 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1115
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1116 bool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1117 if (CoaLimitActive) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1118 if (CoaCounter >= CoaLimit)
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1119 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1120 CoaCounter++;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1121 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1122 unsigned BW1, BW2;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1123 if (!isIntReg(R1, BW1) \|\| !isIntReg(R2, BW2) \|\| BW1 != BW2)
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1124 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1125 if (MRI->isLiveIn(R1.Reg))
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1126 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1127 if (MRI->isLiveIn(R2.Reg))
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1128 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1129
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1130 LiveInterval &L1 = LIS->getInterval(R1.Reg);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1131 LiveInterval &L2 = LIS->getInterval(R2.Reg);
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1132 if (L2.empty())
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1133 return false;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1134 if (L1.hasSubRanges() \|\| L2.hasSubRanges())
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1135 return false;
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1136 bool Overlap = L1.overlaps(L2);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1137
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1138 DEBUG(dbgs() << "compatible registers: ("
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1139 << (Overlap ? "overlap" : "disjoint") << ")\n "
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1140 << PrintReg(R1.Reg, TRI, R1.Sub) << " " << L1 << "\n "
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1141 << PrintReg(R2.Reg, TRI, R2.Sub) << " " << L2 << "\n");
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1142 if (R1.Sub \|\| R2.Sub)
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1143 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1144 if (Overlap)
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1145 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1146
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1147 // Coalescing could have a negative impact on scheduling, so try to limit
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1148 // to some reasonable extent. Only consider coalescing segments, when one
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1149 // of them does not cross basic block boundaries.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1150 if (!isIntraBlocks(L1) && !isIntraBlocks(L2))
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1151 return false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1152
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1153 MRI->replaceRegWith(R2.Reg, R1.Reg);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1154
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1155 // Move all live segments from L2 to L1.
121 803732b1fca8 LLVM 5.0 kono parents: 120 diff changeset	1156 using ValueInfoMap = DenseMap<VNInfo , VNInfo >;
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1157 ValueInfoMap VM;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1158 for (LiveInterval::iterator I = L2.begin(), E = L2.end(); I != E; ++I) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1159 VNInfo NewVN, OldVN = I->valno;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1160 ValueInfoMap::iterator F = VM.find(OldVN);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1161 if (F == VM.end()) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1162 NewVN = L1.getNextValue(I->valno->def, LIS->getVNInfoAllocator());
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1163 VM.insert(std::make_pair(OldVN, NewVN));
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1164 } else {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1165 NewVN = F->second;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1166 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1167 L1.addSegment(LiveRange::Segment(I->start, I->end, NewVN));
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1168 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1169 while (L2.begin() != L2.end())
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1170 L2.removeSegment(*L2.begin());
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1171 LIS->removeInterval(R2.Reg);
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1172
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1173 updateKillFlags(R1.Reg);
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1174 DEBUG(dbgs() << "coalesced: " << L1 << "\n");
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1175 L1.verify();
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1176
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1177 return true;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1178 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1179
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1180 /// Attempt to coalesce one of the source registers to a MUX instruction with
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1181 /// the destination register. This could lead to having only one predicated
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1182 /// instruction in the end instead of two.
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1183 bool HexagonExpandCondsets::coalesceSegments(
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1184 const SmallVectorImpl<MachineInstr*> &Condsets,
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1185 std::set<unsigned> &UpdRegs) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1186 SmallVector<MachineInstr*,16> TwoRegs;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1187 for (MachineInstr *MI : Condsets) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1188 MachineOperand &S1 = MI->getOperand(2), &S2 = MI->getOperand(3);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1189 if (!S1.isReg() && !S2.isReg())
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1190 continue;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1191 TwoRegs.push_back(MI);
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1192 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1193
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1194 bool Changed = false;
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1195 for (MachineInstr *CI : TwoRegs) {
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1196 RegisterRef RD = CI->getOperand(0);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1197 RegisterRef RP = CI->getOperand(1);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1198 MachineOperand &S1 = CI->getOperand(2), &S2 = CI->getOperand(3);
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1199 bool Done = false;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1200 // Consider this case:
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1201 // vreg1 = instr1 ...
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1202 // vreg2 = instr2 ...
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1203 // vreg0 = C2_mux ..., vreg1, vreg2
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1204 // If vreg0 was coalesced with vreg1, we could end up with the following
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1205 // code:
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1206 // vreg0 = instr1 ...
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1207 // vreg2 = instr2 ...
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1208 // vreg0 = A2_tfrf ..., vreg2
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1209 // which will later become:
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1210 // vreg0 = instr1 ...
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1211 // vreg0 = instr2_cNotPt ...
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1212 // i.e. there will be an unconditional definition (instr1) of vreg0
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1213 // followed by a conditional one. The output dependency was there before
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1214 // and it unavoidable, but if instr1 is predicable, we will no longer be
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1215 // able to predicate it here.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1216 // To avoid this scenario, don't coalesce the destination register with
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1217 // a source register that is defined by a predicable instruction.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1218 if (S1.isReg()) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1219 RegisterRef RS = S1;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1220 MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg, true);
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1221 if (!RDef \|\| !HII->isPredicable(*RDef)) {
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1222 Done = coalesceRegisters(RD, RegisterRef(S1));
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1223 if (Done) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1224 UpdRegs.insert(RD.Reg);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1225 UpdRegs.insert(S1.getReg());
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1226 }
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1227 }
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1228 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1229 if (!Done && S2.isReg()) {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1230 RegisterRef RS = S2;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1231 MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg, false);
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1232 if (!RDef \|\| !HII->isPredicable(*RDef)) {
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1233 Done = coalesceRegisters(RD, RegisterRef(S2));
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1234 if (Done) {
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1235 UpdRegs.insert(RD.Reg);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1236 UpdRegs.insert(S2.getReg());
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1237 }
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1238 }
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1239 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1240 Changed \|= Done;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1241 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1242 return Changed;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1243 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1244
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1245 bool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) {
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1246 if (skipFunction(*MF.getFunction()))
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1247 return false;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1248
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1249 HII = static_cast<const HexagonInstrInfo*>(MF.getSubtarget().getInstrInfo());
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1250 TRI = MF.getSubtarget().getRegisterInfo();
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1251 MDT = &getAnalysis<MachineDominatorTree>();
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1252 LIS = &getAnalysis<LiveIntervals>();
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1253 MRI = &MF.getRegInfo();
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1254
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1255 DEBUG(LIS->print(dbgs() << "Before expand-condsets\n",
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1256 MF.getFunction()->getParent()));
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1257
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1258 bool Changed = false;
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1259 std::set<unsigned> CoalUpd, PredUpd;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1260
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1261 SmallVector<MachineInstr*,16> Condsets;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1262 for (auto &B : MF)
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1263 for (auto &I : B)
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1264 if (isCondset(I))
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1265 Condsets.push_back(&I);
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1266
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1267 // Try to coalesce the target of a mux with one of its sources.
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1268 // This could eliminate a register copy in some circumstances.
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1269 Changed \|= coalesceSegments(Condsets, CoalUpd);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1270
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1271 // Update kill flags on all source operands. This is done here because
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1272 // at this moment (when expand-condsets runs), there are no kill flags
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1273 // in the IR (they have been removed by live range analysis).
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1274 // Updating them right before we split is the easiest, because splitting
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1275 // adds definitions which would interfere with updating kills afterwards.
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1276 std::set<unsigned> KillUpd;
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1277 for (MachineInstr *MI : Condsets)
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1278 for (MachineOperand &Op : MI->operands())
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1279 if (Op.isReg() && Op.isUse())
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1280 if (!CoalUpd.count(Op.getReg()))
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1281 KillUpd.insert(Op.getReg());
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1282 updateLiveness(KillUpd, false, true, false);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1283 DEBUG(LIS->print(dbgs() << "After coalescing\n",
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1284 MF.getFunction()->getParent()));
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1285
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1286 // First, simply split all muxes into a pair of conditional transfers
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1287 // and update the live intervals to reflect the new arrangement. The
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1288 // goal is to update the kill flags, since predication will rely on
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1289 // them.
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1290 for (MachineInstr *MI : Condsets)
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1291 Changed \|= split(*MI, PredUpd);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1292 Condsets.clear(); // The contents of Condsets are invalid here anyway.
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1293
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1294 // Do not update live ranges after splitting. Recalculation of live
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1295 // intervals removes kill flags, which were preserved by splitting on
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1296 // the source operands of condsets. These kill flags are needed by
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1297 // predication, and after splitting they are difficult to recalculate
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1298 // (because of predicated defs), so make sure they are left untouched.
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1299 // Predication does not use live intervals.
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1300 DEBUG(LIS->print(dbgs() << "After splitting\n",
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1301 MF.getFunction()->getParent()));
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1302
120 1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1303 // Traverse all blocks and collapse predicable instructions feeding
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1304 // conditional transfers into predicated instructions.
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1305 // Walk over all the instructions again, so we may catch pre-existing
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1306 // cases that were not created in the previous step.
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1307 for (auto &B : MF)
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1308 Changed \|= predicateInBlock(B, PredUpd);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1309 DEBUG(LIS->print(dbgs() << "After predicating\n",
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1310 MF.getFunction()->getParent()));
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1311
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1312 PredUpd.insert(CoalUpd.begin(), CoalUpd.end());
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1313 updateLiveness(PredUpd, true, true, true);
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1314
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1315 DEBUG({
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1316 if (Changed)
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1317 LIS->print(dbgs() << "After expand-condsets\n",
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1318 MF.getFunction()->getParent());
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1319 });
1172e4bd9c6f update 4.0.0 mir3636 parents: 95 diff changeset	1320
95 afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1321 return Changed;
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1322 }
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1323
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1324 //===----------------------------------------------------------------------===//
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1325 // Public Constructor Functions
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1326 //===----------------------------------------------------------------------===//
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1327
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1328 FunctionPass *llvm::createHexagonExpandCondsets() {
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1329 return new HexagonExpandCondsets();
afa8332a0e37 LLVM 3.8 Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp> parents: diff changeset	1330 }

Mercurial > hg > CbC > CbC_llvm

annotate lib/Target/Hexagon/HexagonExpandCondsets.cpp @ 121:803732b1fca8