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1 //===-- PeepholeOptimizer.cpp - Peephole Optimizations --------------------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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4 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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10 // Perform peephole optimizations on the machine code:
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11 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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12 // - Optimize Extensions
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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13 //
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14 // Optimization of sign / zero extension instructions. It may be extended to
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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15 // handle other instructions with similar properties.
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16 //
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17 // On some targets, some instructions, e.g. X86 sign / zero extension, may
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18 // leave the source value in the lower part of the result. This optimization
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19 // will replace some uses of the pre-extension value with uses of the
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20 // sub-register of the results.
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21 //
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22 // - Optimize Comparisons
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23 //
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24 // Optimization of comparison instructions. For instance, in this code:
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25 //
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26 // sub r1, 1
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27 // cmp r1, 0
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28 // bz L1
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29 //
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30 // If the "sub" instruction all ready sets (or could be modified to set) the
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31 // same flag that the "cmp" instruction sets and that "bz" uses, then we can
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32 // eliminate the "cmp" instruction.
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33 //
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34 // Another instance, in this code:
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35 //
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36 // sub r1, r3 | sub r1, imm
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37 // cmp r3, r1 or cmp r1, r3 | cmp r1, imm
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38 // bge L1
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39 //
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40 // If the branch instruction can use flag from "sub", then we can replace
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41 // "sub" with "subs" and eliminate the "cmp" instruction.
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42 //
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43 // - Optimize Loads:
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44 //
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45 // Loads that can be folded into a later instruction. A load is foldable
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46 // if it loads to virtual registers and the virtual register defined has
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47 // a single use.
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48 //
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77
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49 // - Optimize Copies and Bitcast (more generally, target specific copies):
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50 //
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51 // Rewrite copies and bitcasts to avoid cross register bank copies
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52 // when possible.
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53 // E.g., Consider the following example, where capital and lower
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54 // letters denote different register file:
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55 // b = copy A <-- cross-bank copy
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56 // C = copy b <-- cross-bank copy
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57 // =>
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58 // b = copy A <-- cross-bank copy
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59 // C = copy A <-- same-bank copy
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60 //
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61 // E.g., for bitcast:
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62 // b = bitcast A <-- cross-bank copy
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63 // C = bitcast b <-- cross-bank copy
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64 // =>
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65 // b = bitcast A <-- cross-bank copy
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66 // C = copy A <-- same-bank copy
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67 //===----------------------------------------------------------------------===//
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68
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69 #include "llvm/CodeGen/Passes.h"
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70 #include "llvm/ADT/DenseMap.h"
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71 #include "llvm/ADT/SmallPtrSet.h"
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72 #include "llvm/ADT/SmallSet.h"
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73 #include "llvm/ADT/Statistic.h"
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74 #include "llvm/CodeGen/MachineDominators.h"
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75 #include "llvm/CodeGen/MachineInstrBuilder.h"
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76 #include "llvm/CodeGen/MachineRegisterInfo.h"
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77 #include "llvm/Support/CommandLine.h"
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78 #include "llvm/Support/Debug.h"
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79 #include "llvm/Target/TargetInstrInfo.h"
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80 #include "llvm/Target/TargetRegisterInfo.h"
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77
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81 #include "llvm/Target/TargetSubtargetInfo.h"
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82 #include <utility>
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83 using namespace llvm;
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84
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85 #define DEBUG_TYPE "peephole-opt"
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86
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87 // Optimize Extensions
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88 static cl::opt<bool>
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89 Aggressive("aggressive-ext-opt", cl::Hidden,
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90 cl::desc("Aggressive extension optimization"));
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91
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92 static cl::opt<bool>
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93 DisablePeephole("disable-peephole", cl::Hidden, cl::init(false),
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94 cl::desc("Disable the peephole optimizer"));
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95
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77
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96 static cl::opt<bool>
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97 DisableAdvCopyOpt("disable-adv-copy-opt", cl::Hidden, cl::init(false),
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98 cl::desc("Disable advanced copy optimization"));
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99
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100 STATISTIC(NumReuse, "Number of extension results reused");
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101 STATISTIC(NumCmps, "Number of compares eliminated");
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102 STATISTIC(NumImmFold, "Number of move immediate folded");
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103 STATISTIC(NumLoadFold, "Number of loads folded");
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104 STATISTIC(NumSelects, "Number of selects optimized");
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77
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105 STATISTIC(NumUncoalescableCopies, "Number of uncoalescable copies optimized");
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106 STATISTIC(NumRewrittenCopies, "Number of copies rewritten");
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107
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108 namespace {
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109 class PeepholeOptimizer : public MachineFunctionPass {
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110 const TargetInstrInfo *TII;
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83
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111 const TargetRegisterInfo *TRI;
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112 MachineRegisterInfo *MRI;
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113 MachineDominatorTree *DT; // Machine dominator tree
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114
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115 public:
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116 static char ID; // Pass identification
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117 PeepholeOptimizer() : MachineFunctionPass(ID) {
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118 initializePeepholeOptimizerPass(*PassRegistry::getPassRegistry());
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119 }
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120
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121 bool runOnMachineFunction(MachineFunction &MF) override;
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122
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123 void getAnalysisUsage(AnalysisUsage &AU) const override {
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124 AU.setPreservesCFG();
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125 MachineFunctionPass::getAnalysisUsage(AU);
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126 if (Aggressive) {
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127 AU.addRequired<MachineDominatorTree>();
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128 AU.addPreserved<MachineDominatorTree>();
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129 }
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130 }
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131
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132 private:
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133 bool optimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB);
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134 bool optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
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77
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135 SmallPtrSetImpl<MachineInstr*> &LocalMIs);
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83
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136 bool optimizeSelect(MachineInstr *MI,
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137 SmallPtrSetImpl<MachineInstr *> &LocalMIs);
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138 bool optimizeCondBranch(MachineInstr *MI);
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139 bool optimizeCopyOrBitcast(MachineInstr *MI);
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77
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140 bool optimizeCoalescableCopy(MachineInstr *MI);
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141 bool optimizeUncoalescableCopy(MachineInstr *MI,
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142 SmallPtrSetImpl<MachineInstr *> &LocalMIs);
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143 bool findNextSource(unsigned &Reg, unsigned &SubReg);
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144 bool isMoveImmediate(MachineInstr *MI,
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145 SmallSet<unsigned, 4> &ImmDefRegs,
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146 DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
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147 bool foldImmediate(MachineInstr *MI, MachineBasicBlock *MBB,
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148 SmallSet<unsigned, 4> &ImmDefRegs,
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149 DenseMap<unsigned, MachineInstr*> &ImmDefMIs);
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77
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150 bool isLoadFoldable(MachineInstr *MI,
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|
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151 SmallSet<unsigned, 16> &FoldAsLoadDefCandidates);
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152
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153 /// \brief Check whether \p MI is understood by the register coalescer
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154 /// but may require some rewriting.
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155 bool isCoalescableCopy(const MachineInstr &MI) {
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156 // SubregToRegs are not interesting, because they are already register
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157 // coalescer friendly.
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158 return MI.isCopy() || (!DisableAdvCopyOpt &&
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159 (MI.isRegSequence() || MI.isInsertSubreg() ||
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160 MI.isExtractSubreg()));
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|
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161 }
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162
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163 /// \brief Check whether \p MI is a copy like instruction that is
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164 /// not recognized by the register coalescer.
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165 bool isUncoalescableCopy(const MachineInstr &MI) {
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166 return MI.isBitcast() ||
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167 (!DisableAdvCopyOpt &&
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168 (MI.isRegSequenceLike() || MI.isInsertSubregLike() ||
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169 MI.isExtractSubregLike()));
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170 }
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171 };
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172
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173 /// \brief Helper class to track the possible sources of a value defined by
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174 /// a (chain of) copy related instructions.
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175 /// Given a definition (instruction and definition index), this class
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176 /// follows the use-def chain to find successive suitable sources.
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177 /// The given source can be used to rewrite the definition into
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178 /// def = COPY src.
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179 ///
|
|
|
180 /// For instance, let us consider the following snippet:
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|
|
181 /// v0 =
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|
|
182 /// v2 = INSERT_SUBREG v1, v0, sub0
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|
|
183 /// def = COPY v2.sub0
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|
184 ///
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|
|
185 /// Using a ValueTracker for def = COPY v2.sub0 will give the following
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|
186 /// suitable sources:
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|
|
187 /// v2.sub0 and v0.
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|
|
188 /// Then, def can be rewritten into def = COPY v0.
|
|
|
189 class ValueTracker {
|
|
|
190 private:
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|
191 /// The current point into the use-def chain.
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|
|
192 const MachineInstr *Def;
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193 /// The index of the definition in Def.
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|
|
194 unsigned DefIdx;
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195 /// The sub register index of the definition.
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|
|
196 unsigned DefSubReg;
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|
197 /// The register where the value can be found.
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|
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198 unsigned Reg;
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199 /// Specifiy whether or not the value tracking looks through
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|
200 /// complex instructions. When this is false, the value tracker
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201 /// bails on everything that is not a copy or a bitcast.
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202 ///
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203 /// Note: This could have been implemented as a specialized version of
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204 /// the ValueTracker class but that would have complicated the code of
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205 /// the users of this class.
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|
|
206 bool UseAdvancedTracking;
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207 /// MachineRegisterInfo used to perform tracking.
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|
|
208 const MachineRegisterInfo &MRI;
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|
209 /// Optional TargetInstrInfo used to perform some complex
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|
210 /// tracking.
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|
|
211 const TargetInstrInfo *TII;
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212
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213 /// \brief Dispatcher to the right underlying implementation of
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|
|
214 /// getNextSource.
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|
|
215 bool getNextSourceImpl(unsigned &SrcReg, unsigned &SrcSubReg);
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|
|
216 /// \brief Specialized version of getNextSource for Copy instructions.
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|
|
217 bool getNextSourceFromCopy(unsigned &SrcReg, unsigned &SrcSubReg);
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|
|
218 /// \brief Specialized version of getNextSource for Bitcast instructions.
|
|
|
219 bool getNextSourceFromBitcast(unsigned &SrcReg, unsigned &SrcSubReg);
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|
|
220 /// \brief Specialized version of getNextSource for RegSequence
|
|
|
221 /// instructions.
|
|
|
222 bool getNextSourceFromRegSequence(unsigned &SrcReg, unsigned &SrcSubReg);
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|
|
223 /// \brief Specialized version of getNextSource for InsertSubreg
|
|
|
224 /// instructions.
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|
|
225 bool getNextSourceFromInsertSubreg(unsigned &SrcReg, unsigned &SrcSubReg);
|
|
|
226 /// \brief Specialized version of getNextSource for ExtractSubreg
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|
227 /// instructions.
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|
|
228 bool getNextSourceFromExtractSubreg(unsigned &SrcReg, unsigned &SrcSubReg);
|
|
|
229 /// \brief Specialized version of getNextSource for SubregToReg
|
|
|
230 /// instructions.
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|
|
231 bool getNextSourceFromSubregToReg(unsigned &SrcReg, unsigned &SrcSubReg);
|
|
|
232
|
|
|
233 public:
|
|
|
234 /// \brief Create a ValueTracker instance for the value defined by \p Reg.
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|
|
235 /// \p DefSubReg represents the sub register index the value tracker will
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|
|
236 /// track. It does not need to match the sub register index used in the
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|
|
237 /// definition of \p Reg.
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|
238 /// \p UseAdvancedTracking specifies whether or not the value tracker looks
|
|
|
239 /// through complex instructions. By default (false), it handles only copy
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|
|
240 /// and bitcast instructions.
|
|
|
241 /// If \p Reg is a physical register, a value tracker constructed with
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|
|
242 /// this constructor will not find any alternative source.
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|
|
243 /// Indeed, when \p Reg is a physical register that constructor does not
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|
|
244 /// know which definition of \p Reg it should track.
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|
|
245 /// Use the next constructor to track a physical register.
|
|
|
246 ValueTracker(unsigned Reg, unsigned DefSubReg,
|
|
|
247 const MachineRegisterInfo &MRI,
|
|
|
248 bool UseAdvancedTracking = false,
|
|
|
249 const TargetInstrInfo *TII = nullptr)
|
|
|
250 : Def(nullptr), DefIdx(0), DefSubReg(DefSubReg), Reg(Reg),
|
|
|
251 UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) {
|
|
|
252 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
|
|
253 Def = MRI.getVRegDef(Reg);
|
|
|
254 DefIdx = MRI.def_begin(Reg).getOperandNo();
|
|
|
255 }
|
|
|
256 }
|
|
|
257
|
|
|
258 /// \brief Create a ValueTracker instance for the value defined by
|
|
|
259 /// the pair \p MI, \p DefIdx.
|
|
|
260 /// Unlike the other constructor, the value tracker produced by this one
|
|
|
261 /// may be able to find a new source when the definition is a physical
|
|
|
262 /// register.
|
|
|
263 /// This could be useful to rewrite target specific instructions into
|
|
|
264 /// generic copy instructions.
|
|
|
265 ValueTracker(const MachineInstr &MI, unsigned DefIdx, unsigned DefSubReg,
|
|
|
266 const MachineRegisterInfo &MRI,
|
|
|
267 bool UseAdvancedTracking = false,
|
|
|
268 const TargetInstrInfo *TII = nullptr)
|
|
|
269 : Def(&MI), DefIdx(DefIdx), DefSubReg(DefSubReg),
|
|
|
270 UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) {
|
|
|
271 assert(DefIdx < Def->getDesc().getNumDefs() &&
|
|
|
272 Def->getOperand(DefIdx).isReg() && "Invalid definition");
|
|
|
273 Reg = Def->getOperand(DefIdx).getReg();
|
|
|
274 }
|
|
|
275
|
|
|
276 /// \brief Following the use-def chain, get the next available source
|
|
|
277 /// for the tracked value.
|
|
|
278 /// When the returned value is not nullptr, \p SrcReg gives the register
|
|
|
279 /// that contain the tracked value.
|
|
|
280 /// \note The sub register index returned in \p SrcSubReg must be used
|
|
|
281 /// on \p SrcReg to access the actual value.
|
|
|
282 /// \return Unless the returned value is nullptr (i.e., no source found),
|
|
|
283 /// \p SrcReg gives the register of the next source used in the returned
|
|
|
284 /// instruction and \p SrcSubReg the sub-register index to be used on that
|
|
|
285 /// source to get the tracked value. When nullptr is returned, no
|
|
|
286 /// alternative source has been found.
|
|
|
287 const MachineInstr *getNextSource(unsigned &SrcReg, unsigned &SrcSubReg);
|
|
|
288
|
|
|
289 /// \brief Get the last register where the initial value can be found.
|
|
|
290 /// Initially this is the register of the definition.
|
|
|
291 /// Then, after each successful call to getNextSource, this is the
|
|
|
292 /// register of the last source.
|
|
|
293 unsigned getReg() const { return Reg; }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
294 };
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
295 }
|
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parents:
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|
296
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
297 char PeepholeOptimizer::ID = 0;
|
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|
298 char &llvm::PeepholeOptimizerID = PeepholeOptimizer::ID;
|
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|
299 INITIALIZE_PASS_BEGIN(PeepholeOptimizer, "peephole-opts",
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
300 "Peephole Optimizations", false, false)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
301 INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
302 INITIALIZE_PASS_END(PeepholeOptimizer, "peephole-opts",
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
303 "Peephole Optimizations", false, false)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
304
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
305 /// optimizeExtInstr - If instruction is a copy-like instruction, i.e. it reads
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
306 /// a single register and writes a single register and it does not modify the
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
307 /// source, and if the source value is preserved as a sub-register of the
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
308 /// result, then replace all reachable uses of the source with the subreg of the
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
309 /// result.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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|
310 ///
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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|
311 /// Do not generate an EXTRACT that is used only in a debug use, as this changes
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
312 /// the code. Since this code does not currently share EXTRACTs, just ignore all
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
313 /// debug uses.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
314 bool PeepholeOptimizer::
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
315 optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
|
|
77
|
316 SmallPtrSetImpl<MachineInstr*> &LocalMIs) {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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diff
changeset
|
317 unsigned SrcReg, DstReg, SubIdx;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
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|
318 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
319 return false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
320
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
321 if (TargetRegisterInfo::isPhysicalRegister(DstReg) ||
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
322 TargetRegisterInfo::isPhysicalRegister(SrcReg))
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
323 return false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
324
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
325 if (MRI->hasOneNonDBGUse(SrcReg))
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
326 // No other uses.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
327 return false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
328
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
329 // Ensure DstReg can get a register class that actually supports
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
330 // sub-registers. Don't change the class until we commit.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
331 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
|
|
83
|
332 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
333 if (!DstRC)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
334 return false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
335
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
336 // The ext instr may be operating on a sub-register of SrcReg as well.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
337 // PPC::EXTSW is a 32 -> 64-bit sign extension, but it reads a 64-bit
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
338 // register.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
339 // If UseSrcSubIdx is Set, SubIdx also applies to SrcReg, and only uses of
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
340 // SrcReg:SubIdx should be replaced.
|
|
77
|
341 bool UseSrcSubIdx =
|
|
83
|
342 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
343
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
344 // The source has other uses. See if we can replace the other uses with use of
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
345 // the result of the extension.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
346 SmallPtrSet<MachineBasicBlock*, 4> ReachedBBs;
|
|
77
|
347 for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg))
|
|
|
348 ReachedBBs.insert(UI.getParent());
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
349
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
350 // Uses that are in the same BB of uses of the result of the instruction.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
351 SmallVector<MachineOperand*, 8> Uses;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
352
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
353 // Uses that the result of the instruction can reach.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
354 SmallVector<MachineOperand*, 8> ExtendedUses;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
355
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
356 bool ExtendLife = true;
|
|
77
|
357 for (MachineOperand &UseMO : MRI->use_nodbg_operands(SrcReg)) {
|
|
|
358 MachineInstr *UseMI = UseMO.getParent();
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
359 if (UseMI == MI)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
360 continue;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
361
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
362 if (UseMI->isPHI()) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
363 ExtendLife = false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
364 continue;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
365 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
366
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
367 // Only accept uses of SrcReg:SubIdx.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
368 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
369 continue;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
370
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
371 // It's an error to translate this:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
372 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
373 // %reg1025 = <sext> %reg1024
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
374 // ...
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
375 // %reg1026 = SUBREG_TO_REG 0, %reg1024, 4
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
376 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
377 // into this:
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
378 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
379 // %reg1025 = <sext> %reg1024
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
380 // ...
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
381 // %reg1027 = COPY %reg1025:4
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
382 // %reg1026 = SUBREG_TO_REG 0, %reg1027, 4
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
383 //
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
384 // The problem here is that SUBREG_TO_REG is there to assert that an
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
385 // implicit zext occurs. It doesn't insert a zext instruction. If we allow
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
386 // the COPY here, it will give us the value after the <sext>, not the
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
387 // original value of %reg1024 before <sext>.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
388 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
389 continue;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
390
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
391 MachineBasicBlock *UseMBB = UseMI->getParent();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
392 if (UseMBB == MBB) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
393 // Local uses that come after the extension.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
394 if (!LocalMIs.count(UseMI))
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
395 Uses.push_back(&UseMO);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
396 } else if (ReachedBBs.count(UseMBB)) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
397 // Non-local uses where the result of the extension is used. Always
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
398 // replace these unless it's a PHI.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
399 Uses.push_back(&UseMO);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
400 } else if (Aggressive && DT->dominates(MBB, UseMBB)) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
401 // We may want to extend the live range of the extension result in order
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
402 // to replace these uses.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
403 ExtendedUses.push_back(&UseMO);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
404 } else {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
405 // Both will be live out of the def MBB anyway. Don't extend live range of
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
406 // the extension result.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
407 ExtendLife = false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
408 break;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
409 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
410 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
411
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
412 if (ExtendLife && !ExtendedUses.empty())
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
413 // Extend the liveness of the extension result.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
414 std::copy(ExtendedUses.begin(), ExtendedUses.end(),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
415 std::back_inserter(Uses));
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
416
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
417 // Now replace all uses.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
418 bool Changed = false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
419 if (!Uses.empty()) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
420 SmallPtrSet<MachineBasicBlock*, 4> PHIBBs;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
421
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
422 // Look for PHI uses of the extended result, we don't want to extend the
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
423 // liveness of a PHI input. It breaks all kinds of assumptions down
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
424 // stream. A PHI use is expected to be the kill of its source values.
|
|
77
|
425 for (MachineInstr &UI : MRI->use_nodbg_instructions(DstReg))
|
|
|
426 if (UI.isPHI())
|
|
|
427 PHIBBs.insert(UI.getParent());
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
428
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
429 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
430 for (unsigned i = 0, e = Uses.size(); i != e; ++i) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
431 MachineOperand *UseMO = Uses[i];
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
432 MachineInstr *UseMI = UseMO->getParent();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
433 MachineBasicBlock *UseMBB = UseMI->getParent();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
434 if (PHIBBs.count(UseMBB))
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
435 continue;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
436
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
437 // About to add uses of DstReg, clear DstReg's kill flags.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
438 if (!Changed) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
439 MRI->clearKillFlags(DstReg);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
440 MRI->constrainRegClass(DstReg, DstRC);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
441 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
442
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
443 unsigned NewVR = MRI->createVirtualRegister(RC);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
444 MachineInstr *Copy = BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
445 TII->get(TargetOpcode::COPY), NewVR)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
446 .addReg(DstReg, 0, SubIdx);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
447 // SubIdx applies to both SrcReg and DstReg when UseSrcSubIdx is set.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
448 if (UseSrcSubIdx) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
449 Copy->getOperand(0).setSubReg(SubIdx);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
450 Copy->getOperand(0).setIsUndef();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
451 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
452 UseMO->setReg(NewVR);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
453 ++NumReuse;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
454 Changed = true;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
455 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
456 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
457
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
458 return Changed;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
459 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
460
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
461 /// optimizeCmpInstr - If the instruction is a compare and the previous
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
462 /// instruction it's comparing against all ready sets (or could be modified to
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
463 /// set) the same flag as the compare, then we can remove the comparison and use
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
464 /// the flag from the previous instruction.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
465 bool PeepholeOptimizer::optimizeCmpInstr(MachineInstr *MI,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
466 MachineBasicBlock *MBB) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
467 // If this instruction is a comparison against zero and isn't comparing a
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
468 // physical register, we can try to optimize it.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
469 unsigned SrcReg, SrcReg2;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
470 int CmpMask, CmpValue;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
471 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) ||
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
472 TargetRegisterInfo::isPhysicalRegister(SrcReg) ||
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
473 (SrcReg2 != 0 && TargetRegisterInfo::isPhysicalRegister(SrcReg2)))
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
474 return false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
475
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
476 // Attempt to optimize the comparison instruction.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
477 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
478 ++NumCmps;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
479 return true;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
480 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
481
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
482 return false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
483 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
484
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
485 /// Optimize a select instruction.
|
|
83
|
486 bool PeepholeOptimizer::optimizeSelect(MachineInstr *MI,
|
|
|
487 SmallPtrSetImpl<MachineInstr *> &LocalMIs) {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
488 unsigned TrueOp = 0;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
489 unsigned FalseOp = 0;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
490 bool Optimizable = false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
491 SmallVector<MachineOperand, 4> Cond;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
492 if (TII->analyzeSelect(MI, Cond, TrueOp, FalseOp, Optimizable))
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
493 return false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
494 if (!Optimizable)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
495 return false;
|
|
83
|
496 if (!TII->optimizeSelect(MI, LocalMIs))
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
497 return false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
498 MI->eraseFromParent();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
499 ++NumSelects;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
500 return true;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
501 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
502
|
|
83
|
503 /// \brief Check if a simpler conditional branch can be
|
|
|
504 // generated
|
|
|
505 bool PeepholeOptimizer::optimizeCondBranch(MachineInstr *MI) {
|
|
|
506 return TII->optimizeCondBranch(MI);
|
|
|
507 }
|
|
|
508
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
509 /// \brief Check if the registers defined by the pair (RegisterClass, SubReg)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
510 /// share the same register file.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
511 static bool shareSameRegisterFile(const TargetRegisterInfo &TRI,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
512 const TargetRegisterClass *DefRC,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
513 unsigned DefSubReg,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
514 const TargetRegisterClass *SrcRC,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
515 unsigned SrcSubReg) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
516 // Same register class.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
517 if (DefRC == SrcRC)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
518 return true;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
519
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
520 // Both operands are sub registers. Check if they share a register class.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
521 unsigned SrcIdx, DefIdx;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
522 if (SrcSubReg && DefSubReg)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
523 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg,
|
|
77
|
524 SrcIdx, DefIdx) != nullptr;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
525 // At most one of the register is a sub register, make it Src to avoid
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
526 // duplicating the test.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
527 if (!SrcSubReg) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
528 std::swap(DefSubReg, SrcSubReg);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
529 std::swap(DefRC, SrcRC);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
530 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
531
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
532 // One of the register is a sub register, check if we can get a superclass.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
533 if (SrcSubReg)
|
|
77
|
534 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
535 // Plain copy.
|
|
77
|
536 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
537 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
538
|
|
77
|
539 /// \brief Try to find the next source that share the same register file
|
|
|
540 /// for the value defined by \p Reg and \p SubReg.
|
|
|
541 /// When true is returned, \p Reg and \p SubReg are updated with the
|
|
|
542 /// register number and sub-register index of the new source.
|
|
|
543 /// \return False if no alternative sources are available. True otherwise.
|
|
|
544 bool PeepholeOptimizer::findNextSource(unsigned &Reg, unsigned &SubReg) {
|
|
|
545 // Do not try to find a new source for a physical register.
|
|
|
546 // So far we do not have any motivating example for doing that.
|
|
|
547 // Thus, instead of maintaining untested code, we will revisit that if
|
|
|
548 // that changes at some point.
|
|
|
549 if (TargetRegisterInfo::isPhysicalRegister(Reg))
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
550 return false;
|
|
77
|
551
|
|
|
552 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg);
|
|
|
553 unsigned DefSubReg = SubReg;
|
|
|
554
|
|
|
555 unsigned Src;
|
|
|
556 unsigned SrcSubReg;
|
|
|
557 bool ShouldRewrite = false;
|
|
|
558
|
|
|
559 // Follow the chain of copies until we reach the top of the use-def chain
|
|
|
560 // or find a more suitable source.
|
|
|
561 ValueTracker ValTracker(Reg, DefSubReg, *MRI, !DisableAdvCopyOpt, TII);
|
|
|
562 do {
|
|
|
563 unsigned CopySrcReg, CopySrcSubReg;
|
|
|
564 if (!ValTracker.getNextSource(CopySrcReg, CopySrcSubReg))
|
|
|
565 break;
|
|
|
566 Src = CopySrcReg;
|
|
|
567 SrcSubReg = CopySrcSubReg;
|
|
|
568
|
|
|
569 // Do not extend the live-ranges of physical registers as they add
|
|
|
570 // constraints to the register allocator.
|
|
|
571 // Moreover, if we want to extend the live-range of a physical register,
|
|
|
572 // unlike SSA virtual register, we will have to check that they are not
|
|
|
573 // redefine before the related use.
|
|
|
574 if (TargetRegisterInfo::isPhysicalRegister(Src))
|
|
|
575 break;
|
|
|
576
|
|
|
577 const TargetRegisterClass *SrcRC = MRI->getRegClass(Src);
|
|
|
578
|
|
|
579 // If this source does not incur a cross register bank copy, use it.
|
|
83
|
580 ShouldRewrite = shareSameRegisterFile(*TRI, DefRC, DefSubReg, SrcRC,
|
|
77
|
581 SrcSubReg);
|
|
|
582 } while (!ShouldRewrite);
|
|
|
583
|
|
|
584 // If we did not find a more suitable source, there is nothing to optimize.
|
|
|
585 if (!ShouldRewrite || Src == Reg)
|
|
|
586 return false;
|
|
|
587
|
|
|
588 Reg = Src;
|
|
|
589 SubReg = SrcSubReg;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
590 return true;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
591 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
592
|
|
77
|
593 namespace {
|
|
|
594 /// \brief Helper class to rewrite the arguments of a copy-like instruction.
|
|
|
595 class CopyRewriter {
|
|
|
596 protected:
|
|
|
597 /// The copy-like instruction.
|
|
|
598 MachineInstr &CopyLike;
|
|
|
599 /// The index of the source being rewritten.
|
|
|
600 unsigned CurrentSrcIdx;
|
|
|
601
|
|
|
602 public:
|
|
|
603 CopyRewriter(MachineInstr &MI) : CopyLike(MI), CurrentSrcIdx(0) {}
|
|
|
604
|
|
|
605 virtual ~CopyRewriter() {}
|
|
|
606
|
|
|
607 /// \brief Get the next rewritable source (SrcReg, SrcSubReg) and
|
|
|
608 /// the related value that it affects (TrackReg, TrackSubReg).
|
|
|
609 /// A source is considered rewritable if its register class and the
|
|
|
610 /// register class of the related TrackReg may not be register
|
|
|
611 /// coalescer friendly. In other words, given a copy-like instruction
|
|
|
612 /// not all the arguments may be returned at rewritable source, since
|
|
|
613 /// some arguments are none to be register coalescer friendly.
|
|
|
614 ///
|
|
|
615 /// Each call of this method moves the current source to the next
|
|
|
616 /// rewritable source.
|
|
|
617 /// For instance, let CopyLike be the instruction to rewrite.
|
|
|
618 /// CopyLike has one definition and one source:
|
|
|
619 /// dst.dstSubIdx = CopyLike src.srcSubIdx.
|
|
|
620 ///
|
|
|
621 /// The first call will give the first rewritable source, i.e.,
|
|
|
622 /// the only source this instruction has:
|
|
|
623 /// (SrcReg, SrcSubReg) = (src, srcSubIdx).
|
|
|
624 /// This source defines the whole definition, i.e.,
|
|
|
625 /// (TrackReg, TrackSubReg) = (dst, dstSubIdx).
|
|
|
626 ///
|
|
|
627 /// The second and subsequent calls will return false, has there is only one
|
|
|
628 /// rewritable source.
|
|
|
629 ///
|
|
|
630 /// \return True if a rewritable source has been found, false otherwise.
|
|
|
631 /// The output arguments are valid if and only if true is returned.
|
|
|
632 virtual bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
|
|
|
633 unsigned &TrackReg,
|
|
|
634 unsigned &TrackSubReg) {
|
|
|
635 // If CurrentSrcIdx == 1, this means this function has already been
|
|
|
636 // called once. CopyLike has one defintiion and one argument, thus,
|
|
|
637 // there is nothing else to rewrite.
|
|
|
638 if (!CopyLike.isCopy() || CurrentSrcIdx == 1)
|
|
|
639 return false;
|
|
|
640 // This is the first call to getNextRewritableSource.
|
|
|
641 // Move the CurrentSrcIdx to remember that we made that call.
|
|
|
642 CurrentSrcIdx = 1;
|
|
|
643 // The rewritable source is the argument.
|
|
|
644 const MachineOperand &MOSrc = CopyLike.getOperand(1);
|
|
|
645 SrcReg = MOSrc.getReg();
|
|
|
646 SrcSubReg = MOSrc.getSubReg();
|
|
|
647 // What we track are the alternative sources of the definition.
|
|
|
648 const MachineOperand &MODef = CopyLike.getOperand(0);
|
|
|
649 TrackReg = MODef.getReg();
|
|
|
650 TrackSubReg = MODef.getSubReg();
|
|
|
651 return true;
|
|
|
652 }
|
|
|
653
|
|
|
654 /// \brief Rewrite the current source with \p NewReg and \p NewSubReg
|
|
|
655 /// if possible.
|
|
|
656 /// \return True if the rewritting was possible, false otherwise.
|
|
|
657 virtual bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) {
|
|
|
658 if (!CopyLike.isCopy() || CurrentSrcIdx != 1)
|
|
|
659 return false;
|
|
|
660 MachineOperand &MOSrc = CopyLike.getOperand(CurrentSrcIdx);
|
|
|
661 MOSrc.setReg(NewReg);
|
|
|
662 MOSrc.setSubReg(NewSubReg);
|
|
|
663 return true;
|
|
|
664 }
|
|
|
665 };
|
|
|
666
|
|
|
667 /// \brief Specialized rewriter for INSERT_SUBREG instruction.
|
|
|
668 class InsertSubregRewriter : public CopyRewriter {
|
|
|
669 public:
|
|
|
670 InsertSubregRewriter(MachineInstr &MI) : CopyRewriter(MI) {
|
|
|
671 assert(MI.isInsertSubreg() && "Invalid instruction");
|
|
|
672 }
|
|
|
673
|
|
|
674 /// \brief See CopyRewriter::getNextRewritableSource.
|
|
|
675 /// Here CopyLike has the following form:
|
|
|
676 /// dst = INSERT_SUBREG Src1, Src2.src2SubIdx, subIdx.
|
|
|
677 /// Src1 has the same register class has dst, hence, there is
|
|
|
678 /// nothing to rewrite.
|
|
|
679 /// Src2.src2SubIdx, may not be register coalescer friendly.
|
|
|
680 /// Therefore, the first call to this method returns:
|
|
|
681 /// (SrcReg, SrcSubReg) = (Src2, src2SubIdx).
|
|
|
682 /// (TrackReg, TrackSubReg) = (dst, subIdx).
|
|
|
683 ///
|
|
|
684 /// Subsequence calls will return false.
|
|
|
685 bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
|
|
|
686 unsigned &TrackReg,
|
|
|
687 unsigned &TrackSubReg) override {
|
|
|
688 // If we already get the only source we can rewrite, return false.
|
|
|
689 if (CurrentSrcIdx == 2)
|
|
|
690 return false;
|
|
|
691 // We are looking at v2 = INSERT_SUBREG v0, v1, sub0.
|
|
|
692 CurrentSrcIdx = 2;
|
|
|
693 const MachineOperand &MOInsertedReg = CopyLike.getOperand(2);
|
|
|
694 SrcReg = MOInsertedReg.getReg();
|
|
|
695 SrcSubReg = MOInsertedReg.getSubReg();
|
|
|
696 const MachineOperand &MODef = CopyLike.getOperand(0);
|
|
|
697
|
|
|
698 // We want to track something that is compatible with the
|
|
|
699 // partial definition.
|
|
|
700 TrackReg = MODef.getReg();
|
|
|
701 if (MODef.getSubReg())
|
|
|
702 // Bails if we have to compose sub-register indices.
|
|
|
703 return false;
|
|
|
704 TrackSubReg = (unsigned)CopyLike.getOperand(3).getImm();
|
|
|
705 return true;
|
|
|
706 }
|
|
|
707 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
|
|
|
708 if (CurrentSrcIdx != 2)
|
|
|
709 return false;
|
|
|
710 // We are rewriting the inserted reg.
|
|
|
711 MachineOperand &MO = CopyLike.getOperand(CurrentSrcIdx);
|
|
|
712 MO.setReg(NewReg);
|
|
|
713 MO.setSubReg(NewSubReg);
|
|
|
714 return true;
|
|
|
715 }
|
|
|
716 };
|
|
|
717
|
|
|
718 /// \brief Specialized rewriter for EXTRACT_SUBREG instruction.
|
|
|
719 class ExtractSubregRewriter : public CopyRewriter {
|
|
|
720 const TargetInstrInfo &TII;
|
|
|
721
|
|
|
722 public:
|
|
|
723 ExtractSubregRewriter(MachineInstr &MI, const TargetInstrInfo &TII)
|
|
|
724 : CopyRewriter(MI), TII(TII) {
|
|
|
725 assert(MI.isExtractSubreg() && "Invalid instruction");
|
|
|
726 }
|
|
|
727
|
|
|
728 /// \brief See CopyRewriter::getNextRewritableSource.
|
|
|
729 /// Here CopyLike has the following form:
|
|
|
730 /// dst.dstSubIdx = EXTRACT_SUBREG Src, subIdx.
|
|
|
731 /// There is only one rewritable source: Src.subIdx,
|
|
|
732 /// which defines dst.dstSubIdx.
|
|
|
733 bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
|
|
|
734 unsigned &TrackReg,
|
|
|
735 unsigned &TrackSubReg) override {
|
|
|
736 // If we already get the only source we can rewrite, return false.
|
|
|
737 if (CurrentSrcIdx == 1)
|
|
|
738 return false;
|
|
|
739 // We are looking at v1 = EXTRACT_SUBREG v0, sub0.
|
|
|
740 CurrentSrcIdx = 1;
|
|
|
741 const MachineOperand &MOExtractedReg = CopyLike.getOperand(1);
|
|
|
742 SrcReg = MOExtractedReg.getReg();
|
|
|
743 // If we have to compose sub-register indices, bails out.
|
|
|
744 if (MOExtractedReg.getSubReg())
|
|
|
745 return false;
|
|
|
746
|
|
|
747 SrcSubReg = CopyLike.getOperand(2).getImm();
|
|
|
748
|
|
|
749 // We want to track something that is compatible with the definition.
|
|
|
750 const MachineOperand &MODef = CopyLike.getOperand(0);
|
|
|
751 TrackReg = MODef.getReg();
|
|
|
752 TrackSubReg = MODef.getSubReg();
|
|
|
753 return true;
|
|
|
754 }
|
|
|
755
|
|
|
756 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
|
|
|
757 // The only source we can rewrite is the input register.
|
|
|
758 if (CurrentSrcIdx != 1)
|
|
|
759 return false;
|
|
|
760
|
|
|
761 CopyLike.getOperand(CurrentSrcIdx).setReg(NewReg);
|
|
|
762
|
|
|
763 // If we find a source that does not require to extract something,
|
|
|
764 // rewrite the operation with a copy.
|
|
|
765 if (!NewSubReg) {
|
|
|
766 // Move the current index to an invalid position.
|
|
|
767 // We do not want another call to this method to be able
|
|
|
768 // to do any change.
|
|
|
769 CurrentSrcIdx = -1;
|
|
|
770 // Rewrite the operation as a COPY.
|
|
|
771 // Get rid of the sub-register index.
|
|
|
772 CopyLike.RemoveOperand(2);
|
|
|
773 // Morph the operation into a COPY.
|
|
|
774 CopyLike.setDesc(TII.get(TargetOpcode::COPY));
|
|
|
775 return true;
|
|
|
776 }
|
|
|
777 CopyLike.getOperand(CurrentSrcIdx + 1).setImm(NewSubReg);
|
|
|
778 return true;
|
|
|
779 }
|
|
|
780 };
|
|
|
781
|
|
|
782 /// \brief Specialized rewriter for REG_SEQUENCE instruction.
|
|
|
783 class RegSequenceRewriter : public CopyRewriter {
|
|
|
784 public:
|
|
|
785 RegSequenceRewriter(MachineInstr &MI) : CopyRewriter(MI) {
|
|
|
786 assert(MI.isRegSequence() && "Invalid instruction");
|
|
|
787 }
|
|
|
788
|
|
|
789 /// \brief See CopyRewriter::getNextRewritableSource.
|
|
|
790 /// Here CopyLike has the following form:
|
|
|
791 /// dst = REG_SEQUENCE Src1.src1SubIdx, subIdx1, Src2.src2SubIdx, subIdx2.
|
|
|
792 /// Each call will return a different source, walking all the available
|
|
|
793 /// source.
|
|
|
794 ///
|
|
|
795 /// The first call returns:
|
|
|
796 /// (SrcReg, SrcSubReg) = (Src1, src1SubIdx).
|
|
|
797 /// (TrackReg, TrackSubReg) = (dst, subIdx1).
|
|
|
798 ///
|
|
|
799 /// The second call returns:
|
|
|
800 /// (SrcReg, SrcSubReg) = (Src2, src2SubIdx).
|
|
|
801 /// (TrackReg, TrackSubReg) = (dst, subIdx2).
|
|
|
802 ///
|
|
|
803 /// And so on, until all the sources have been traversed, then
|
|
|
804 /// it returns false.
|
|
|
805 bool getNextRewritableSource(unsigned &SrcReg, unsigned &SrcSubReg,
|
|
|
806 unsigned &TrackReg,
|
|
|
807 unsigned &TrackSubReg) override {
|
|
|
808 // We are looking at v0 = REG_SEQUENCE v1, sub1, v2, sub2, etc.
|
|
|
809
|
|
|
810 // If this is the first call, move to the first argument.
|
|
|
811 if (CurrentSrcIdx == 0) {
|
|
|
812 CurrentSrcIdx = 1;
|
|
|
813 } else {
|
|
|
814 // Otherwise, move to the next argument and check that it is valid.
|
|
|
815 CurrentSrcIdx += 2;
|
|
|
816 if (CurrentSrcIdx >= CopyLike.getNumOperands())
|
|
|
817 return false;
|
|
|
818 }
|
|
|
819 const MachineOperand &MOInsertedReg = CopyLike.getOperand(CurrentSrcIdx);
|
|
|
820 SrcReg = MOInsertedReg.getReg();
|
|
|
821 // If we have to compose sub-register indices, bails out.
|
|
|
822 if ((SrcSubReg = MOInsertedReg.getSubReg()))
|
|
|
823 return false;
|
|
|
824
|
|
|
825 // We want to track something that is compatible with the related
|
|
|
826 // partial definition.
|
|
|
827 TrackSubReg = CopyLike.getOperand(CurrentSrcIdx + 1).getImm();
|
|
|
828
|
|
|
829 const MachineOperand &MODef = CopyLike.getOperand(0);
|
|
|
830 TrackReg = MODef.getReg();
|
|
|
831 // If we have to compose sub-registers, bails.
|
|
|
832 return MODef.getSubReg() == 0;
|
|
|
833 }
|
|
|
834
|
|
|
835 bool RewriteCurrentSource(unsigned NewReg, unsigned NewSubReg) override {
|
|
|
836 // We cannot rewrite out of bound operands.
|
|
|
837 // Moreover, rewritable sources are at odd positions.
|
|
|
838 if ((CurrentSrcIdx & 1) != 1 || CurrentSrcIdx > CopyLike.getNumOperands())
|
|
|
839 return false;
|
|
|
840
|
|
|
841 MachineOperand &MO = CopyLike.getOperand(CurrentSrcIdx);
|
|
|
842 MO.setReg(NewReg);
|
|
|
843 MO.setSubReg(NewSubReg);
|
|
|
844 return true;
|
|
|
845 }
|
|
|
846 };
|
|
|
847 } // End namespace.
|
|
|
848
|
|
|
849 /// \brief Get the appropriated CopyRewriter for \p MI.
|
|
|
850 /// \return A pointer to a dynamically allocated CopyRewriter or nullptr
|
|
|
851 /// if no rewriter works for \p MI.
|
|
|
852 static CopyRewriter *getCopyRewriter(MachineInstr &MI,
|
|
|
853 const TargetInstrInfo &TII) {
|
|
|
854 switch (MI.getOpcode()) {
|
|
|
855 default:
|
|
|
856 return nullptr;
|
|
|
857 case TargetOpcode::COPY:
|
|
|
858 return new CopyRewriter(MI);
|
|
|
859 case TargetOpcode::INSERT_SUBREG:
|
|
|
860 return new InsertSubregRewriter(MI);
|
|
|
861 case TargetOpcode::EXTRACT_SUBREG:
|
|
|
862 return new ExtractSubregRewriter(MI, TII);
|
|
|
863 case TargetOpcode::REG_SEQUENCE:
|
|
|
864 return new RegSequenceRewriter(MI);
|
|
|
865 }
|
|
|
866 llvm_unreachable(nullptr);
|
|
|
867 }
|
|
|
868
|
|
|
869 /// \brief Optimize generic copy instructions to avoid cross
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
870 /// register bank copy. The optimization looks through a chain of
|
|
77
|
871 /// copies and tries to find a source that has a compatible register
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
872 /// class.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
873 /// Two register classes are considered to be compatible if they share
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
874 /// the same register bank.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
875 /// New copies issued by this optimization are register allocator
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
876 /// friendly. This optimization does not remove any copy as it may
|
|
77
|
877 /// overconstraint the register allocator, but replaces some operands
|
|
|
878 /// when possible.
|
|
|
879 /// \pre isCoalescableCopy(*MI) is true.
|
|
|
880 /// \return True, when \p MI has been rewritten. False otherwise.
|
|
|
881 bool PeepholeOptimizer::optimizeCoalescableCopy(MachineInstr *MI) {
|
|
|
882 assert(MI && isCoalescableCopy(*MI) && "Invalid argument");
|
|
|
883 assert(MI->getDesc().getNumDefs() == 1 &&
|
|
|
884 "Coalescer can understand multiple defs?!");
|
|
|
885 const MachineOperand &MODef = MI->getOperand(0);
|
|
|
886 // Do not rewrite physical definitions.
|
|
|
887 if (TargetRegisterInfo::isPhysicalRegister(MODef.getReg()))
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
888 return false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
889
|
|
77
|
890 bool Changed = false;
|
|
|
891 // Get the right rewriter for the current copy.
|
|
|
892 std::unique_ptr<CopyRewriter> CpyRewriter(getCopyRewriter(*MI, *TII));
|
|
|
893 // If none exists, bails out.
|
|
|
894 if (!CpyRewriter)
|
|
|
895 return false;
|
|
|
896 // Rewrite each rewritable source.
|
|
|
897 unsigned SrcReg, SrcSubReg, TrackReg, TrackSubReg;
|
|
|
898 while (CpyRewriter->getNextRewritableSource(SrcReg, SrcSubReg, TrackReg,
|
|
|
899 TrackSubReg)) {
|
|
|
900 unsigned NewSrc = TrackReg;
|
|
|
901 unsigned NewSubReg = TrackSubReg;
|
|
|
902 // Try to find a more suitable source.
|
|
|
903 // If we failed to do so, or get the actual source,
|
|
|
904 // move to the next source.
|
|
|
905 if (!findNextSource(NewSrc, NewSubReg) || SrcReg == NewSrc)
|
|
|
906 continue;
|
|
|
907 // Rewrite source.
|
|
|
908 if (CpyRewriter->RewriteCurrentSource(NewSrc, NewSubReg)) {
|
|
|
909 // We may have extended the live-range of NewSrc, account for that.
|
|
|
910 MRI->clearKillFlags(NewSrc);
|
|
|
911 Changed = true;
|
|
|
912 }
|
|
|
913 }
|
|
|
914 // TODO: We could have a clean-up method to tidy the instruction.
|
|
|
915 // E.g., v0 = INSERT_SUBREG v1, v1.sub0, sub0
|
|
|
916 // => v0 = COPY v1
|
|
|
917 // Currently we haven't seen motivating example for that and we
|
|
|
918 // want to avoid untested code.
|
|
|
919 NumRewrittenCopies += Changed == true;
|
|
|
920 return Changed;
|
|
|
921 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
922
|
|
77
|
923 /// \brief Optimize copy-like instructions to create
|
|
|
924 /// register coalescer friendly instruction.
|
|
|
925 /// The optimization tries to kill-off the \p MI by looking
|
|
|
926 /// through a chain of copies to find a source that has a compatible
|
|
|
927 /// register class.
|
|
|
928 /// If such a source is found, it replace \p MI by a generic COPY
|
|
|
929 /// operation.
|
|
|
930 /// \pre isUncoalescableCopy(*MI) is true.
|
|
|
931 /// \return True, when \p MI has been optimized. In that case, \p MI has
|
|
|
932 /// been removed from its parent.
|
|
|
933 /// All COPY instructions created, are inserted in \p LocalMIs.
|
|
|
934 bool PeepholeOptimizer::optimizeUncoalescableCopy(
|
|
|
935 MachineInstr *MI, SmallPtrSetImpl<MachineInstr *> &LocalMIs) {
|
|
|
936 assert(MI && isUncoalescableCopy(*MI) && "Invalid argument");
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
937
|
|
77
|
938 // Check if we can rewrite all the values defined by this instruction.
|
|
|
939 SmallVector<
|
|
|
940 std::pair<TargetInstrInfo::RegSubRegPair, TargetInstrInfo::RegSubRegPair>,
|
|
|
941 4> RewritePairs;
|
|
|
942 for (const MachineOperand &MODef : MI->defs()) {
|
|
|
943 if (MODef.isDead())
|
|
|
944 // We can ignore those.
|
|
|
945 continue;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
946
|
|
77
|
947 // If a physical register is here, this is probably for a good reason.
|
|
|
948 // Do not rewrite that.
|
|
|
949 if (TargetRegisterInfo::isPhysicalRegister(MODef.getReg()))
|
|
|
950 return false;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
951
|
|
77
|
952 // If we do not know how to rewrite this definition, there is no point
|
|
|
953 // in trying to kill this instruction.
|
|
|
954 TargetInstrInfo::RegSubRegPair Def(MODef.getReg(), MODef.getSubReg());
|
|
|
955 TargetInstrInfo::RegSubRegPair Src = Def;
|
|
|
956 if (!findNextSource(Src.Reg, Src.SubReg))
|
|
|
957 return false;
|
|
|
958 RewritePairs.push_back(std::make_pair(Def, Src));
|
|
|
959 }
|
|
|
960 // The change is possible for all defs, do it.
|
|
|
961 for (const auto &PairDefSrc : RewritePairs) {
|
|
|
962 const auto &Def = PairDefSrc.first;
|
|
|
963 const auto &Src = PairDefSrc.second;
|
|
|
964 // Rewrite the "copy" in a way the register coalescer understands.
|
|
|
965 assert(!TargetRegisterInfo::isPhysicalRegister(Def.Reg) &&
|
|
|
966 "We do not rewrite physical registers");
|
|
|
967 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg);
|
|
|
968 unsigned NewVR = MRI->createVirtualRegister(DefRC);
|
|
|
969 MachineInstr *NewCopy = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
|
|
|
970 TII->get(TargetOpcode::COPY),
|
|
|
971 NewVR).addReg(Src.Reg, 0, Src.SubReg);
|
|
|
972 NewCopy->getOperand(0).setSubReg(Def.SubReg);
|
|
|
973 if (Def.SubReg)
|
|
|
974 NewCopy->getOperand(0).setIsUndef();
|
|
|
975 LocalMIs.insert(NewCopy);
|
|
|
976 MRI->replaceRegWith(Def.Reg, NewVR);
|
|
|
977 MRI->clearKillFlags(NewVR);
|
|
|
978 // We extended the lifetime of Src.
|
|
|
979 // Clear the kill flags to account for that.
|
|
|
980 MRI->clearKillFlags(Src.Reg);
|
|
|
981 }
|
|
|
982 // MI is now dead.
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
983 MI->eraseFromParent();
|
|
77
|
984 ++NumUncoalescableCopies;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
985 return true;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
986 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
987
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
988 /// isLoadFoldable - Check whether MI is a candidate for folding into a later
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
989 /// instruction. We only fold loads to virtual registers and the virtual
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
990 /// register defined has a single use.
|
|
77
|
991 bool PeepholeOptimizer::isLoadFoldable(
|
|
|
992 MachineInstr *MI,
|
|
|
993 SmallSet<unsigned, 16> &FoldAsLoadDefCandidates) {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
994 if (!MI->canFoldAsLoad() || !MI->mayLoad())
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
995 return false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
996 const MCInstrDesc &MCID = MI->getDesc();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
997 if (MCID.getNumDefs() != 1)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
998 return false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
999
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1000 unsigned Reg = MI->getOperand(0).getReg();
|
|
77
|
1001 // To reduce compilation time, we check MRI->hasOneNonDBGUse when inserting
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1002 // loads. It should be checked when processing uses of the load, since
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1003 // uses can be removed during peephole.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1004 if (!MI->getOperand(0).getSubReg() &&
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1005 TargetRegisterInfo::isVirtualRegister(Reg) &&
|
|
77
|
1006 MRI->hasOneNonDBGUse(Reg)) {
|
|
|
1007 FoldAsLoadDefCandidates.insert(Reg);
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1008 return true;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1009 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1010 return false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1011 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1012
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1013 bool PeepholeOptimizer::isMoveImmediate(MachineInstr *MI,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1014 SmallSet<unsigned, 4> &ImmDefRegs,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1015 DenseMap<unsigned, MachineInstr*> &ImmDefMIs) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1016 const MCInstrDesc &MCID = MI->getDesc();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1017 if (!MI->isMoveImmediate())
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1018 return false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1019 if (MCID.getNumDefs() != 1)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1020 return false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1021 unsigned Reg = MI->getOperand(0).getReg();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1022 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1023 ImmDefMIs.insert(std::make_pair(Reg, MI));
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1024 ImmDefRegs.insert(Reg);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1025 return true;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1026 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1027
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1028 return false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1029 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1030
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1031 /// foldImmediate - Try folding register operands that are defined by move
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1032 /// immediate instructions, i.e. a trivial constant folding optimization, if
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1033 /// and only if the def and use are in the same BB.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1034 bool PeepholeOptimizer::foldImmediate(MachineInstr *MI, MachineBasicBlock *MBB,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1035 SmallSet<unsigned, 4> &ImmDefRegs,
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1036 DenseMap<unsigned, MachineInstr*> &ImmDefMIs) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1037 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1038 MachineOperand &MO = MI->getOperand(i);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1039 if (!MO.isReg() || MO.isDef())
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1040 continue;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1041 unsigned Reg = MO.getReg();
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1042 if (!TargetRegisterInfo::isVirtualRegister(Reg))
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1043 continue;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1044 if (ImmDefRegs.count(Reg) == 0)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1045 continue;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1046 DenseMap<unsigned, MachineInstr*>::iterator II = ImmDefMIs.find(Reg);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1047 assert(II != ImmDefMIs.end());
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1048 if (TII->FoldImmediate(MI, II->second, Reg, MRI)) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1049 ++NumImmFold;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1050 return true;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1051 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1052 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1053 return false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1054 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1055
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1056 bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
|
|
77
|
1057 if (skipOptnoneFunction(*MF.getFunction()))
|
|
|
1058 return false;
|
|
|
1059
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1060 DEBUG(dbgs() << "********** PEEPHOLE OPTIMIZER **********\n");
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1061 DEBUG(dbgs() << "********** Function: " << MF.getName() << '\n');
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1062
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1063 if (DisablePeephole)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1064 return false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1065
|
|
83
|
1066 TII = MF.getSubtarget().getInstrInfo();
|
|
|
1067 TRI = MF.getSubtarget().getRegisterInfo();
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1068 MRI = &MF.getRegInfo();
|
|
77
|
1069 DT = Aggressive ? &getAnalysis<MachineDominatorTree>() : nullptr;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1070
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1071 bool Changed = false;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1072
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1073 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1074 MachineBasicBlock *MBB = &*I;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1075
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1076 bool SeenMoveImm = false;
|
|
83
|
1077
|
|
|
1078 // During this forward scan, at some point it needs to answer the question
|
|
|
1079 // "given a pointer to an MI in the current BB, is it located before or
|
|
|
1080 // after the current instruction".
|
|
|
1081 // To perform this, the following set keeps track of the MIs already seen
|
|
|
1082 // during the scan, if a MI is not in the set, it is assumed to be located
|
|
|
1083 // after. Newly created MIs have to be inserted in the set as well.
|
|
77
|
1084 SmallPtrSet<MachineInstr*, 16> LocalMIs;
|
|
|
1085 SmallSet<unsigned, 4> ImmDefRegs;
|
|
|
1086 DenseMap<unsigned, MachineInstr*> ImmDefMIs;
|
|
|
1087 SmallSet<unsigned, 16> FoldAsLoadDefCandidates;
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1088
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1089 for (MachineBasicBlock::iterator
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1090 MII = I->begin(), MIE = I->end(); MII != MIE; ) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1091 MachineInstr *MI = &*MII;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1092 // We may be erasing MI below, increment MII now.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1093 ++MII;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1094 LocalMIs.insert(MI);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1095
|
|
77
|
1096 // Skip debug values. They should not affect this peephole optimization.
|
|
|
1097 if (MI->isDebugValue())
|
|
|
1098 continue;
|
|
|
1099
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1100 // If there exists an instruction which belongs to the following
|
|
77
|
1101 // categories, we will discard the load candidates.
|
|
|
1102 if (MI->isPosition() || MI->isPHI() || MI->isImplicitDef() ||
|
|
|
1103 MI->isKill() || MI->isInlineAsm() ||
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1104 MI->hasUnmodeledSideEffects()) {
|
|
77
|
1105 FoldAsLoadDefCandidates.clear();
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1106 continue;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1107 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1108 if (MI->mayStore() || MI->isCall())
|
|
77
|
1109 FoldAsLoadDefCandidates.clear();
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1110
|
|
77
|
1111 if ((isUncoalescableCopy(*MI) &&
|
|
|
1112 optimizeUncoalescableCopy(MI, LocalMIs)) ||
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1113 (MI->isCompare() && optimizeCmpInstr(MI, MBB)) ||
|
|
83
|
1114 (MI->isSelect() && optimizeSelect(MI, LocalMIs))) {
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1115 // MI is deleted.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1116 LocalMIs.erase(MI);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1117 Changed = true;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1118 continue;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1119 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1120
|
|
83
|
1121 if (MI->isConditionalBranch() && optimizeCondBranch(MI)) {
|
|
|
1122 Changed = true;
|
|
|
1123 continue;
|
|
|
1124 }
|
|
|
1125
|
|
77
|
1126 if (isCoalescableCopy(*MI) && optimizeCoalescableCopy(MI)) {
|
|
|
1127 // MI is just rewritten.
|
|
|
1128 Changed = true;
|
|
|
1129 continue;
|
|
|
1130 }
|
|
|
1131
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1132 if (isMoveImmediate(MI, ImmDefRegs, ImmDefMIs)) {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1133 SeenMoveImm = true;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1134 } else {
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1135 Changed |= optimizeExtInstr(MI, MBB, LocalMIs);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1136 // optimizeExtInstr might have created new instructions after MI
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1137 // and before the already incremented MII. Adjust MII so that the
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1138 // next iteration sees the new instructions.
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1139 MII = MI;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1140 ++MII;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1141 if (SeenMoveImm)
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1142 Changed |= foldImmediate(MI, MBB, ImmDefRegs, ImmDefMIs);
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1143 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1144
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1145 // Check whether MI is a load candidate for folding into a later
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1146 // instruction. If MI is not a candidate, check whether we can fold an
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1147 // earlier load into MI.
|
|
77
|
1148 if (!isLoadFoldable(MI, FoldAsLoadDefCandidates) &&
|
|
|
1149 !FoldAsLoadDefCandidates.empty()) {
|
|
|
1150 const MCInstrDesc &MIDesc = MI->getDesc();
|
|
|
1151 for (unsigned i = MIDesc.getNumDefs(); i != MIDesc.getNumOperands();
|
|
|
1152 ++i) {
|
|
|
1153 const MachineOperand &MOp = MI->getOperand(i);
|
|
|
1154 if (!MOp.isReg())
|
|
|
1155 continue;
|
|
|
1156 unsigned FoldAsLoadDefReg = MOp.getReg();
|
|
|
1157 if (FoldAsLoadDefCandidates.count(FoldAsLoadDefReg)) {
|
|
|
1158 // We need to fold load after optimizeCmpInstr, since
|
|
|
1159 // optimizeCmpInstr can enable folding by converting SUB to CMP.
|
|
|
1160 // Save FoldAsLoadDefReg because optimizeLoadInstr() resets it and
|
|
|
1161 // we need it for markUsesInDebugValueAsUndef().
|
|
|
1162 unsigned FoldedReg = FoldAsLoadDefReg;
|
|
|
1163 MachineInstr *DefMI = nullptr;
|
|
|
1164 MachineInstr *FoldMI = TII->optimizeLoadInstr(MI, MRI,
|
|
|
1165 FoldAsLoadDefReg,
|
|
|
1166 DefMI);
|
|
|
1167 if (FoldMI) {
|
|
|
1168 // Update LocalMIs since we replaced MI with FoldMI and deleted
|
|
|
1169 // DefMI.
|
|
|
1170 DEBUG(dbgs() << "Replacing: " << *MI);
|
|
|
1171 DEBUG(dbgs() << " With: " << *FoldMI);
|
|
|
1172 LocalMIs.erase(MI);
|
|
|
1173 LocalMIs.erase(DefMI);
|
|
|
1174 LocalMIs.insert(FoldMI);
|
|
|
1175 MI->eraseFromParent();
|
|
|
1176 DefMI->eraseFromParent();
|
|
|
1177 MRI->markUsesInDebugValueAsUndef(FoldedReg);
|
|
|
1178 FoldAsLoadDefCandidates.erase(FoldedReg);
|
|
|
1179 ++NumLoadFold;
|
|
|
1180 // MI is replaced with FoldMI.
|
|
|
1181 Changed = true;
|
|
|
1182 break;
|
|
|
1183 }
|
|
|
1184 }
|
0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1185 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1186 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1187 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1188 }
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1189
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1190 return Changed;
|
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
|
1191 }
|
|
77
|
1192
|
|
|
1193 bool ValueTracker::getNextSourceFromCopy(unsigned &SrcReg,
|
|
|
1194 unsigned &SrcSubReg) {
|
|
|
1195 assert(Def->isCopy() && "Invalid definition");
|
|
|
1196 // Copy instruction are supposed to be: Def = Src.
|
|
|
1197 // If someone breaks this assumption, bad things will happen everywhere.
|
|
|
1198 assert(Def->getNumOperands() == 2 && "Invalid number of operands");
|
|
|
1199
|
|
|
1200 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
|
|
|
1201 // If we look for a different subreg, it means we want a subreg of src.
|
|
|
1202 // Bails as we do not support composing subreg yet.
|
|
|
1203 return false;
|
|
|
1204 // Otherwise, we want the whole source.
|
|
|
1205 const MachineOperand &Src = Def->getOperand(1);
|
|
|
1206 SrcReg = Src.getReg();
|
|
|
1207 SrcSubReg = Src.getSubReg();
|
|
|
1208 return true;
|
|
|
1209 }
|
|
|
1210
|
|
|
1211 bool ValueTracker::getNextSourceFromBitcast(unsigned &SrcReg,
|
|
|
1212 unsigned &SrcSubReg) {
|
|
|
1213 assert(Def->isBitcast() && "Invalid definition");
|
|
|
1214
|
|
|
1215 // Bail if there are effects that a plain copy will not expose.
|
|
|
1216 if (Def->hasUnmodeledSideEffects())
|
|
|
1217 return false;
|
|
|
1218
|
|
|
1219 // Bitcasts with more than one def are not supported.
|
|
|
1220 if (Def->getDesc().getNumDefs() != 1)
|
|
|
1221 return false;
|
|
|
1222 if (Def->getOperand(DefIdx).getSubReg() != DefSubReg)
|
|
|
1223 // If we look for a different subreg, it means we want a subreg of the src.
|
|
|
1224 // Bails as we do not support composing subreg yet.
|
|
|
1225 return false;
|
|
|
1226
|
|
|
1227 unsigned SrcIdx = Def->getNumOperands();
|
|
|
1228 for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx;
|
|
|
1229 ++OpIdx) {
|
|
|
1230 const MachineOperand &MO = Def->getOperand(OpIdx);
|
|
|
1231 if (!MO.isReg() || !MO.getReg())
|
|
|
1232 continue;
|
|
|
1233 assert(!MO.isDef() && "We should have skipped all the definitions by now");
|
|
|
1234 if (SrcIdx != EndOpIdx)
|
|
|
1235 // Multiple sources?
|
|
|
1236 return false;
|
|
|
1237 SrcIdx = OpIdx;
|
|
|
1238 }
|
|
|
1239 const MachineOperand &Src = Def->getOperand(SrcIdx);
|
|
|
1240 SrcReg = Src.getReg();
|
|
|
1241 SrcSubReg = Src.getSubReg();
|
|
|
1242 return true;
|
|
|
1243 }
|
|
|
1244
|
|
|
1245 bool ValueTracker::getNextSourceFromRegSequence(unsigned &SrcReg,
|
|
|
1246 unsigned &SrcSubReg) {
|
|
|
1247 assert((Def->isRegSequence() || Def->isRegSequenceLike()) &&
|
|
|
1248 "Invalid definition");
|
|
|
1249
|
|
|
1250 if (Def->getOperand(DefIdx).getSubReg())
|
|
|
1251 // If we are composing subreg, bails out.
|
|
|
1252 // The case we are checking is Def.<subreg> = REG_SEQUENCE.
|
|
|
1253 // This should almost never happen as the SSA property is tracked at
|
|
|
1254 // the register level (as opposed to the subreg level).
|
|
|
1255 // I.e.,
|
|
|
1256 // Def.sub0 =
|
|
|
1257 // Def.sub1 =
|
|
|
1258 // is a valid SSA representation for Def.sub0 and Def.sub1, but not for
|
|
|
1259 // Def. Thus, it must not be generated.
|
|
|
1260 // However, some code could theoretically generates a single
|
|
|
1261 // Def.sub0 (i.e, not defining the other subregs) and we would
|
|
|
1262 // have this case.
|
|
|
1263 // If we can ascertain (or force) that this never happens, we could
|
|
|
1264 // turn that into an assertion.
|
|
|
1265 return false;
|
|
|
1266
|
|
|
1267 if (!TII)
|
|
|
1268 // We could handle the REG_SEQUENCE here, but we do not want to
|
|
|
1269 // duplicate the code from the generic TII.
|
|
|
1270 return false;
|
|
|
1271
|
|
|
1272 SmallVector<TargetInstrInfo::RegSubRegPairAndIdx, 8> RegSeqInputRegs;
|
|
|
1273 if (!TII->getRegSequenceInputs(*Def, DefIdx, RegSeqInputRegs))
|
|
|
1274 return false;
|
|
|
1275
|
|
|
1276 // We are looking at:
|
|
|
1277 // Def = REG_SEQUENCE v0, sub0, v1, sub1, ...
|
|
|
1278 // Check if one of the operand defines the subreg we are interested in.
|
|
|
1279 for (auto &RegSeqInput : RegSeqInputRegs) {
|
|
|
1280 if (RegSeqInput.SubIdx == DefSubReg) {
|
|
|
1281 if (RegSeqInput.SubReg)
|
|
|
1282 // Bails if we have to compose sub registers.
|
|
|
1283 return false;
|
|
|
1284
|
|
|
1285 SrcReg = RegSeqInput.Reg;
|
|
|
1286 SrcSubReg = RegSeqInput.SubReg;
|
|
|
1287 return true;
|
|
|
1288 }
|
|
|
1289 }
|
|
|
1290
|
|
|
1291 // If the subreg we are tracking is super-defined by another subreg,
|
|
|
1292 // we could follow this value. However, this would require to compose
|
|
|
1293 // the subreg and we do not do that for now.
|
|
|
1294 return false;
|
|
|
1295 }
|
|
|
1296
|
|
|
1297 bool ValueTracker::getNextSourceFromInsertSubreg(unsigned &SrcReg,
|
|
|
1298 unsigned &SrcSubReg) {
|
|
|
1299 assert((Def->isInsertSubreg() || Def->isInsertSubregLike()) &&
|
|
|
1300 "Invalid definition");
|
|
|
1301
|
|
|
1302 if (Def->getOperand(DefIdx).getSubReg())
|
|
|
1303 // If we are composing subreg, bails out.
|
|
|
1304 // Same remark as getNextSourceFromRegSequence.
|
|
|
1305 // I.e., this may be turned into an assert.
|
|
|
1306 return false;
|
|
|
1307
|
|
|
1308 if (!TII)
|
|
|
1309 // We could handle the REG_SEQUENCE here, but we do not want to
|
|
|
1310 // duplicate the code from the generic TII.
|
|
|
1311 return false;
|
|
|
1312
|
|
|
1313 TargetInstrInfo::RegSubRegPair BaseReg;
|
|
|
1314 TargetInstrInfo::RegSubRegPairAndIdx InsertedReg;
|
|
|
1315 if (!TII->getInsertSubregInputs(*Def, DefIdx, BaseReg, InsertedReg))
|
|
|
1316 return false;
|
|
|
1317
|
|
|
1318 // We are looking at:
|
|
|
1319 // Def = INSERT_SUBREG v0, v1, sub1
|
|
|
1320 // There are two cases:
|
|
|
1321 // 1. DefSubReg == sub1, get v1.
|
|
|
1322 // 2. DefSubReg != sub1, the value may be available through v0.
|
|
|
1323
|
|
|
1324 // #1 Check if the inserted register matches the required sub index.
|
|
|
1325 if (InsertedReg.SubIdx == DefSubReg) {
|
|
|
1326 SrcReg = InsertedReg.Reg;
|
|
|
1327 SrcSubReg = InsertedReg.SubReg;
|
|
|
1328 return true;
|
|
|
1329 }
|
|
|
1330 // #2 Otherwise, if the sub register we are looking for is not partial
|
|
|
1331 // defined by the inserted element, we can look through the main
|
|
|
1332 // register (v0).
|
|
|
1333 const MachineOperand &MODef = Def->getOperand(DefIdx);
|
|
|
1334 // If the result register (Def) and the base register (v0) do not
|
|
|
1335 // have the same register class or if we have to compose
|
|
|
1336 // subregisters, bails out.
|
|
|
1337 if (MRI.getRegClass(MODef.getReg()) != MRI.getRegClass(BaseReg.Reg) ||
|
|
|
1338 BaseReg.SubReg)
|
|
|
1339 return false;
|
|
|
1340
|
|
|
1341 // Get the TRI and check if the inserted sub-register overlaps with the
|
|
|
1342 // sub-register we are tracking.
|
|
|
1343 const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
|
|
|
1344 if (!TRI ||
|
|
|
1345 (TRI->getSubRegIndexLaneMask(DefSubReg) &
|
|
|
1346 TRI->getSubRegIndexLaneMask(InsertedReg.SubIdx)) != 0)
|
|
|
1347 return false;
|
|
|
1348 // At this point, the value is available in v0 via the same subreg
|
|
|
1349 // we used for Def.
|
|
|
1350 SrcReg = BaseReg.Reg;
|
|
|
1351 SrcSubReg = DefSubReg;
|
|
|
1352 return true;
|
|
|
1353 }
|
|
|
1354
|
|
|
1355 bool ValueTracker::getNextSourceFromExtractSubreg(unsigned &SrcReg,
|
|
|
1356 unsigned &SrcSubReg) {
|
|
|
1357 assert((Def->isExtractSubreg() ||
|
|
|
1358 Def->isExtractSubregLike()) && "Invalid definition");
|
|
|
1359 // We are looking at:
|
|
|
1360 // Def = EXTRACT_SUBREG v0, sub0
|
|
|
1361
|
|
|
1362 // Bails if we have to compose sub registers.
|
|
|
1363 // Indeed, if DefSubReg != 0, we would have to compose it with sub0.
|
|
|
1364 if (DefSubReg)
|
|
|
1365 return false;
|
|
|
1366
|
|
|
1367 if (!TII)
|
|
|
1368 // We could handle the EXTRACT_SUBREG here, but we do not want to
|
|
|
1369 // duplicate the code from the generic TII.
|
|
|
1370 return false;
|
|
|
1371
|
|
|
1372 TargetInstrInfo::RegSubRegPairAndIdx ExtractSubregInputReg;
|
|
|
1373 if (!TII->getExtractSubregInputs(*Def, DefIdx, ExtractSubregInputReg))
|
|
|
1374 return false;
|
|
|
1375
|
|
|
1376 // Bails if we have to compose sub registers.
|
|
|
1377 // Likewise, if v0.subreg != 0, we would have to compose v0.subreg with sub0.
|
|
|
1378 if (ExtractSubregInputReg.SubReg)
|
|
|
1379 return false;
|
|
|
1380 // Otherwise, the value is available in the v0.sub0.
|
|
|
1381 SrcReg = ExtractSubregInputReg.Reg;
|
|
|
1382 SrcSubReg = ExtractSubregInputReg.SubIdx;
|
|
|
1383 return true;
|
|
|
1384 }
|
|
|
1385
|
|
|
1386 bool ValueTracker::getNextSourceFromSubregToReg(unsigned &SrcReg,
|
|
|
1387 unsigned &SrcSubReg) {
|
|
|
1388 assert(Def->isSubregToReg() && "Invalid definition");
|
|
|
1389 // We are looking at:
|
|
|
1390 // Def = SUBREG_TO_REG Imm, v0, sub0
|
|
|
1391
|
|
|
1392 // Bails if we have to compose sub registers.
|
|
|
1393 // If DefSubReg != sub0, we would have to check that all the bits
|
|
|
1394 // we track are included in sub0 and if yes, we would have to
|
|
|
1395 // determine the right subreg in v0.
|
|
|
1396 if (DefSubReg != Def->getOperand(3).getImm())
|
|
|
1397 return false;
|
|
|
1398 // Bails if we have to compose sub registers.
|
|
|
1399 // Likewise, if v0.subreg != 0, we would have to compose it with sub0.
|
|
|
1400 if (Def->getOperand(2).getSubReg())
|
|
|
1401 return false;
|
|
|
1402
|
|
|
1403 SrcReg = Def->getOperand(2).getReg();
|
|
|
1404 SrcSubReg = Def->getOperand(3).getImm();
|
|
|
1405 return true;
|
|
|
1406 }
|
|
|
1407
|
|
|
1408 bool ValueTracker::getNextSourceImpl(unsigned &SrcReg, unsigned &SrcSubReg) {
|
|
|
1409 assert(Def && "This method needs a valid definition");
|
|
|
1410
|
|
|
1411 assert(
|
|
|
1412 (DefIdx < Def->getDesc().getNumDefs() || Def->getDesc().isVariadic()) &&
|
|
|
1413 Def->getOperand(DefIdx).isDef() && "Invalid DefIdx");
|
|
|
1414 if (Def->isCopy())
|
|
|
1415 return getNextSourceFromCopy(SrcReg, SrcSubReg);
|
|
|
1416 if (Def->isBitcast())
|
|
|
1417 return getNextSourceFromBitcast(SrcReg, SrcSubReg);
|
|
|
1418 // All the remaining cases involve "complex" instructions.
|
|
|
1419 // Bails if we did not ask for the advanced tracking.
|
|
|
1420 if (!UseAdvancedTracking)
|
|
|
1421 return false;
|
|
|
1422 if (Def->isRegSequence() || Def->isRegSequenceLike())
|
|
|
1423 return getNextSourceFromRegSequence(SrcReg, SrcSubReg);
|
|
|
1424 if (Def->isInsertSubreg() || Def->isInsertSubregLike())
|
|
|
1425 return getNextSourceFromInsertSubreg(SrcReg, SrcSubReg);
|
|
|
1426 if (Def->isExtractSubreg() || Def->isExtractSubregLike())
|
|
|
1427 return getNextSourceFromExtractSubreg(SrcReg, SrcSubReg);
|
|
|
1428 if (Def->isSubregToReg())
|
|
|
1429 return getNextSourceFromSubregToReg(SrcReg, SrcSubReg);
|
|
|
1430 return false;
|
|
|
1431 }
|
|
|
1432
|
|
|
1433 const MachineInstr *ValueTracker::getNextSource(unsigned &SrcReg,
|
|
|
1434 unsigned &SrcSubReg) {
|
|
|
1435 // If we reach a point where we cannot move up in the use-def chain,
|
|
|
1436 // there is nothing we can get.
|
|
|
1437 if (!Def)
|
|
|
1438 return nullptr;
|
|
|
1439
|
|
|
1440 const MachineInstr *PrevDef = nullptr;
|
|
|
1441 // Try to find the next source.
|
|
|
1442 if (getNextSourceImpl(SrcReg, SrcSubReg)) {
|
|
|
1443 // Update definition, definition index, and subregister for the
|
|
|
1444 // next call of getNextSource.
|
|
|
1445 // Update the current register.
|
|
|
1446 Reg = SrcReg;
|
|
|
1447 // Update the return value before moving up in the use-def chain.
|
|
|
1448 PrevDef = Def;
|
|
|
1449 // If we can still move up in the use-def chain, move to the next
|
|
|
1450 // defintion.
|
|
|
1451 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) {
|
|
|
1452 Def = MRI.getVRegDef(Reg);
|
|
|
1453 DefIdx = MRI.def_begin(Reg).getOperandNo();
|
|
|
1454 DefSubReg = SrcSubReg;
|
|
|
1455 return PrevDef;
|
|
|
1456 }
|
|
|
1457 }
|
|
|
1458 // If we end up here, this means we will not be able to find another source
|
|
|
1459 // for the next iteration.
|
|
|
1460 // Make sure any new call to getNextSource bails out early by cutting the
|
|
|
1461 // use-def chain.
|
|
|
1462 Def = nullptr;
|
|
|
1463 return PrevDef;
|
|
|
1464 }
|
