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1 //===-- PPCScheduleE500mc.td - e500mc Scheduling Defs ------*- tablegen -*-===//
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2 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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3 // The LLVM Compiler Infrastructure
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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4 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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7 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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8 //===----------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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9 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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10 // This file defines the itinerary class data for the Freescale e500mc 32-bit
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11 // Power processor.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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12 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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13 // All information is derived from the "e500mc Core Reference Manual",
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14 // Freescale Document Number E500MCRM, Rev. 1, 03/2012.
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15 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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16 //===----------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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17 // Relevant functional units in the Freescale e500mc core:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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18 //
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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19 // * Decode & Dispatch
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20 // Can dispatch up to 2 instructions per clock cycle to either the GPR Issue
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21 // queues (GIQx), FP Issue Queue (FIQ), or Branch issue queue (BIQ).
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33
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22 def E500_DIS0 : FuncUnit; // Dispatch stage - insn 1
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23 def E500_DIS1 : FuncUnit; // Dispatch stage - insn 2
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24
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25 // * Execute
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26 // 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
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27 // Some instructions can only execute in SFX0 but not SFX1.
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28 // The CFX has a bypass path, allowing non-divide instructions to execute
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29 // while a divide instruction is executed.
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33
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30 def E500_SFX0 : FuncUnit; // Simple unit 0
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31 def E500_SFX1 : FuncUnit; // Simple unit 1
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32 def E500_BU : FuncUnit; // Branch unit
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33 def E500_CFX_DivBypass
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34 : FuncUnit; // CFX divide bypass path
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35 def E500_CFX_0 : FuncUnit; // CFX pipeline
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36 def E500_LSU_0 : FuncUnit; // LSU pipeline
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37 def E500_FPU_0 : FuncUnit; // FPU pipeline
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38
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33
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39 def E500_GPR_Bypass : Bypass;
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40 def E500_FPR_Bypass : Bypass;
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41 def E500_CR_Bypass : Bypass;
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42
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43 def PPCE500mcItineraries : ProcessorItineraries<
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33
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44 [E500_DIS0, E500_DIS1, E500_SFX0, E500_SFX1, E500_BU, E500_CFX_DivBypass,
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45 E500_CFX_0, E500_LSU_0, E500_FPU_0],
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46 [E500_CR_Bypass, E500_GPR_Bypass, E500_FPR_Bypass], [
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47 InstrItinData<IIC_IntSimple, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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48 InstrStage<1, [E500_SFX0, E500_SFX1]>],
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49 [4, 1, 1], // Latency = 1
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50 [E500_GPR_Bypass,
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51 E500_GPR_Bypass, E500_GPR_Bypass]>,
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52 InstrItinData<IIC_IntGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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53 InstrStage<1, [E500_SFX0, E500_SFX1]>],
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54 [4, 1, 1], // Latency = 1
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55 [E500_GPR_Bypass,
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56 E500_GPR_Bypass, E500_GPR_Bypass]>,
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83
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57 InstrItinData<IIC_IntISEL, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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58 InstrStage<1, [E500_SFX0, E500_SFX1]>],
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59 [4, 1, 1, 1], // Latency = 1
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60 [E500_GPR_Bypass,
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61 E500_GPR_Bypass, E500_GPR_Bypass,
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62 E500_CR_Bypass]>,
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33
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63 InstrItinData<IIC_IntCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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64 InstrStage<1, [E500_SFX0, E500_SFX1]>],
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65 [5, 1, 1], // Latency = 1 or 2
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66 [E500_CR_Bypass,
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67 E500_GPR_Bypass, E500_GPR_Bypass]>,
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68 InstrItinData<IIC_IntDivW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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69 InstrStage<1, [E500_CFX_0], 0>,
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70 InstrStage<14, [E500_CFX_DivBypass]>],
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71 [17, 1, 1], // Latency=4..35, Repeat= 4..35
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72 [E500_GPR_Bypass,
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73 E500_GPR_Bypass, E500_GPR_Bypass]>,
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74 InstrItinData<IIC_IntMFFS, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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75 InstrStage<8, [E500_FPU_0]>],
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76 [11], // Latency = 8
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77 [E500_FPR_Bypass]>,
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78 InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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79 InstrStage<8, [E500_FPU_0]>],
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80 [11, 1, 1], // Latency = 8
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81 [NoBypass, NoBypass, NoBypass]>,
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82 InstrItinData<IIC_IntMulHW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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83 InstrStage<1, [E500_CFX_0]>],
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84 [7, 1, 1], // Latency = 4, Repeat rate = 1
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85 [E500_GPR_Bypass,
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86 E500_GPR_Bypass, E500_GPR_Bypass]>,
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87 InstrItinData<IIC_IntMulHWU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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88 InstrStage<1, [E500_CFX_0]>],
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89 [7, 1, 1], // Latency = 4, Repeat rate = 1
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90 [E500_GPR_Bypass,
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91 E500_GPR_Bypass, E500_GPR_Bypass]>,
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92 InstrItinData<IIC_IntMulLI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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93 InstrStage<1, [E500_CFX_0]>],
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94 [7, 1, 1], // Latency = 4, Repeat rate = 1
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95 [E500_GPR_Bypass,
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96 E500_GPR_Bypass, E500_GPR_Bypass]>,
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97 InstrItinData<IIC_IntRotate, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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98 InstrStage<1, [E500_SFX0, E500_SFX1]>],
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99 [4, 1, 1], // Latency = 1
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100 [E500_GPR_Bypass,
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101 E500_GPR_Bypass, E500_GPR_Bypass]>,
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102 InstrItinData<IIC_IntShift, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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103 InstrStage<1, [E500_SFX0, E500_SFX1]>],
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104 [4, 1, 1], // Latency = 1
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105 [E500_GPR_Bypass,
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106 E500_GPR_Bypass, E500_GPR_Bypass]>,
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107 InstrItinData<IIC_IntTrapW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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108 InstrStage<2, [E500_SFX0]>],
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109 [5, 1], // Latency = 2, Repeat rate = 2
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110 [E500_GPR_Bypass, E500_GPR_Bypass]>,
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111 InstrItinData<IIC_BrB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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112 InstrStage<1, [E500_BU]>],
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113 [4, 1], // Latency = 1
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114 [NoBypass, E500_GPR_Bypass]>,
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115 InstrItinData<IIC_BrCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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116 InstrStage<1, [E500_BU]>],
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117 [4, 1, 1], // Latency = 1
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118 [E500_CR_Bypass,
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119 E500_CR_Bypass, E500_CR_Bypass]>,
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120 InstrItinData<IIC_BrMCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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121 InstrStage<1, [E500_BU]>],
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122 [4, 1], // Latency = 1
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123 [E500_CR_Bypass, E500_CR_Bypass]>,
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124 InstrItinData<IIC_BrMCRX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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125 InstrStage<1, [E500_SFX0, E500_SFX1]>],
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126 [4, 1, 1], // Latency = 1
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127 [E500_CR_Bypass, E500_GPR_Bypass]>,
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128 InstrItinData<IIC_LdStDCBA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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129 InstrStage<1, [E500_LSU_0]>],
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130 [6, 1], // Latency = 3, Repeat rate = 1
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131 [E500_GPR_Bypass, E500_GPR_Bypass]>,
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132 InstrItinData<IIC_LdStDCBF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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133 InstrStage<1, [E500_LSU_0]>],
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134 [6, 1], // Latency = 3
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135 [E500_GPR_Bypass, E500_GPR_Bypass]>,
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136 InstrItinData<IIC_LdStDCBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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137 InstrStage<1, [E500_LSU_0]>],
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138 [6, 1], // Latency = 3
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139 [E500_GPR_Bypass, E500_GPR_Bypass]>,
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140 InstrItinData<IIC_LdStLoad, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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141 InstrStage<1, [E500_LSU_0]>],
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142 [6, 1], // Latency = 3
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143 [E500_GPR_Bypass, E500_GPR_Bypass]>,
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144 InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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145 InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
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146 InstrStage<1, [E500_LSU_0]>],
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147 [6, 1], // Latency = 3
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148 [E500_GPR_Bypass, E500_GPR_Bypass],
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149 2>, // 2 micro-ops
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150 InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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151 InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
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152 InstrStage<1, [E500_LSU_0]>],
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153 [6, 1], // Latency = 3
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154 [E500_GPR_Bypass, E500_GPR_Bypass],
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155 2>, // 2 micro-ops
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156 InstrItinData<IIC_LdStStore, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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157 InstrStage<1, [E500_LSU_0]>],
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158 [6, 1], // Latency = 3
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159 [NoBypass, E500_GPR_Bypass]>,
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160 InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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161 InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
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162 InstrStage<1, [E500_LSU_0]>],
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163 [6, 1], // Latency = 3
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164 [NoBypass, E500_GPR_Bypass],
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165 2>, // 2 micro-ops
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166 InstrItinData<IIC_LdStICBI, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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167 InstrStage<1, [E500_LSU_0]>],
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168 [6, 1], // Latency = 3
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169 [NoBypass, E500_GPR_Bypass]>,
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170 InstrItinData<IIC_LdStSTFD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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171 InstrStage<1, [E500_LSU_0]>],
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172 [6, 1, 1], // Latency = 3
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173 [E500_GPR_Bypass,
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174 E500_GPR_Bypass, E500_GPR_Bypass]>,
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175 InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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176 InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
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177 InstrStage<1, [E500_LSU_0]>],
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178 [6, 1, 1], // Latency = 3
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179 [E500_GPR_Bypass,
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180 E500_GPR_Bypass, E500_GPR_Bypass],
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181 2>, // 2 micro-ops
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182 InstrItinData<IIC_LdStLFD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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183 InstrStage<1, [E500_LSU_0]>],
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184 [7, 1, 1], // Latency = 4
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185 [E500_FPR_Bypass,
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186 E500_GPR_Bypass, E500_GPR_Bypass]>,
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187 InstrItinData<IIC_LdStLFDU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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188 InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
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189 InstrStage<1, [E500_LSU_0]>],
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190 [7, 1, 1], // Latency = 4
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191 [E500_FPR_Bypass,
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192 E500_GPR_Bypass, E500_GPR_Bypass],
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193 2>, // 2 micro-ops
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194 InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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195 InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
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196 InstrStage<1, [E500_LSU_0]>],
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197 [7, 1, 1], // Latency = 4
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198 [E500_FPR_Bypass,
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199 E500_GPR_Bypass, E500_GPR_Bypass],
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200 2>, // 2 micro-ops
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201 InstrItinData<IIC_LdStLHA, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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202 InstrStage<1, [E500_LSU_0]>],
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203 [6, 1], // Latency = 3
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204 [E500_GPR_Bypass, E500_GPR_Bypass]>,
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205 InstrItinData<IIC_LdStLHAU, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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206 InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
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207 InstrStage<1, [E500_LSU_0]>],
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208 [6, 1], // Latency = 3
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209 [E500_GPR_Bypass, E500_GPR_Bypass]>,
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210 InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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211 InstrStage<1, [E500_SFX0, E500_SFX1], 0>,
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212 InstrStage<1, [E500_LSU_0]>],
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213 [6, 1], // Latency = 3
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214 [E500_GPR_Bypass, E500_GPR_Bypass]>,
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215 InstrItinData<IIC_LdStLMW, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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216 InstrStage<1, [E500_LSU_0]>],
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217 [7, 1], // Latency = r+3
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218 [NoBypass, E500_GPR_Bypass]>,
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219 InstrItinData<IIC_LdStLWARX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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220 InstrStage<3, [E500_LSU_0]>],
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221 [6, 1, 1], // Latency = 3, Repeat rate = 3
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222 [E500_GPR_Bypass,
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223 E500_GPR_Bypass, E500_GPR_Bypass]>,
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224 InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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225 InstrStage<1, [E500_LSU_0]>],
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226 [6, 1], // Latency = 3
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227 [NoBypass, E500_GPR_Bypass]>,
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228 InstrItinData<IIC_LdStSync, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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229 InstrStage<1, [E500_LSU_0]>]>,
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230 InstrItinData<IIC_SprMFSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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231 InstrStage<4, [E500_SFX0]>],
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232 [7, 1],
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233 [E500_GPR_Bypass, E500_GPR_Bypass]>,
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234 InstrItinData<IIC_SprMTMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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235 InstrStage<2, [E500_SFX0, E500_SFX1]>],
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236 [5, 1], // Latency = 2, Repeat rate = 4
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237 [E500_GPR_Bypass, E500_GPR_Bypass]>,
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238 InstrItinData<IIC_SprMTSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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239 InstrStage<1, [E500_SFX0]>],
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240 [5, 1],
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241 [NoBypass, E500_GPR_Bypass]>,
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242 InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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243 InstrStage<1, [E500_LSU_0], 0>]>,
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244 InstrItinData<IIC_SprMFCR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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245 InstrStage<5, [E500_SFX0]>],
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246 [8, 1],
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247 [E500_GPR_Bypass, E500_CR_Bypass]>,
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248 InstrItinData<IIC_SprMFCRF, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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249 InstrStage<5, [E500_SFX0]>],
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250 [8, 1],
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251 [E500_GPR_Bypass, E500_CR_Bypass]>,
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252 InstrItinData<IIC_SprMFMSR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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253 InstrStage<4, [E500_SFX0]>],
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254 [7, 1], // Latency = 4, Repeat rate = 4
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255 [E500_GPR_Bypass, E500_GPR_Bypass]>,
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256 InstrItinData<IIC_SprMFSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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257 InstrStage<1, [E500_SFX0, E500_SFX1]>],
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258 [4, 1], // Latency = 1, Repeat rate = 1
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259 [E500_GPR_Bypass, E500_CR_Bypass]>,
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260 InstrItinData<IIC_SprMFTB, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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261 InstrStage<4, [E500_SFX0]>],
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262 [7, 1], // Latency = 4, Repeat rate = 4
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263 [NoBypass, E500_GPR_Bypass]>,
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264 InstrItinData<IIC_SprMTSPR, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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265 InstrStage<1, [E500_SFX0, E500_SFX1]>],
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266 [4, 1], // Latency = 1, Repeat rate = 1
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267 [E500_CR_Bypass, E500_GPR_Bypass]>,
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268 InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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269 InstrStage<1, [E500_SFX0]>],
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270 [4, 1],
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271 [NoBypass, E500_GPR_Bypass]>,
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272 InstrItinData<IIC_FPGeneral, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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273 InstrStage<2, [E500_FPU_0]>],
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274 [11, 1, 1], // Latency = 8, Repeat rate = 2
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275 [E500_FPR_Bypass,
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276 E500_FPR_Bypass, E500_FPR_Bypass]>,
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277 InstrItinData<IIC_FPAddSub, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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278 InstrStage<4, [E500_FPU_0]>],
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279 [13, 1, 1], // Latency = 10, Repeat rate = 4
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280 [E500_FPR_Bypass,
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281 E500_FPR_Bypass, E500_FPR_Bypass]>,
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282 InstrItinData<IIC_FPCompare, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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283 InstrStage<2, [E500_FPU_0]>],
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284 [11, 1, 1], // Latency = 8, Repeat rate = 2
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285 [E500_CR_Bypass,
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286 E500_FPR_Bypass, E500_FPR_Bypass]>,
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287 InstrItinData<IIC_FPDivD, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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288 InstrStage<68, [E500_FPU_0]>],
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289 [71, 1, 1], // Latency = 68, Repeat rate = 68
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290 [E500_FPR_Bypass,
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291 E500_FPR_Bypass, E500_FPR_Bypass]>,
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292 InstrItinData<IIC_FPDivS, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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293 InstrStage<38, [E500_FPU_0]>],
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294 [41, 1, 1], // Latency = 38, Repeat rate = 38
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295 [E500_FPR_Bypass,
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296 E500_FPR_Bypass, E500_FPR_Bypass]>,
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297 InstrItinData<IIC_FPFused, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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298 InstrStage<4, [E500_FPU_0]>],
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299 [13, 1, 1, 1], // Latency = 10, Repeat rate = 4
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300 [E500_FPR_Bypass,
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301 E500_FPR_Bypass, E500_FPR_Bypass,
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302 E500_FPR_Bypass]>,
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303 InstrItinData<IIC_FPRes, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
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304 InstrStage<38, [E500_FPU_0]>],
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305 [41, 1], // Latency = 38, Repeat rate = 38
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306 [E500_FPR_Bypass, E500_FPR_Bypass]>
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0
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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307 ]>;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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changeset
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308
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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309 // ===---------------------------------------------------------------------===//
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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310 // e500mc machine model for scheduling and other instruction cost heuristics.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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changeset
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311
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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312 def PPCE500mcModel : SchedMachineModel {
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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313 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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314 let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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changeset
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315 let LoadLatency = 5; // Optimistic load latency assuming bypass.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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316 // This is overriden by OperandCycles if the
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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317 // Itineraries are queried instead.
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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changeset
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318
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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319 let Itineraries = PPCE500mcItineraries;
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff
changeset
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320 }
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