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annotate lib/Target/ARM/ARMBaseInstrInfo.h @ 0:95c75e76d11b LLVM3.4

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LLVM 3.4
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Thu, 12 Dec 2013 13:56:28 +0900
parents
children e4204d083e25
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1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #ifndef ARMBASEINSTRUCTIONINFO_H
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15 #define ARMBASEINSTRUCTIONINFO_H
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16
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17 #include "ARM.h"
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18 #include "llvm/ADT/DenseMap.h"
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19 #include "llvm/ADT/SmallSet.h"
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20 #include "llvm/CodeGen/MachineInstrBuilder.h"
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21 #include "llvm/Target/TargetInstrInfo.h"
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22
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23 #define GET_INSTRINFO_HEADER
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24 #include "ARMGenInstrInfo.inc"
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25
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26 namespace llvm {
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27 class ARMSubtarget;
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28 class ARMBaseRegisterInfo;
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29
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30 class ARMBaseInstrInfo : public ARMGenInstrInfo {
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31 const ARMSubtarget &Subtarget;
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32
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33 protected:
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34 // Can be only subclassed.
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35 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
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36
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37 public:
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38 // Return whether the target has an explicit NOP encoding.
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39 bool hasNOP() const;
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40
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41 // Return the non-pre/post incrementing version of 'Opc'. Return 0
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42 // if there is not such an opcode.
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43 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0;
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44
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45 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
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46 MachineBasicBlock::iterator &MBBI,
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47 LiveVariables *LV) const;
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48
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49 virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
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50 const ARMSubtarget &getSubtarget() const { return Subtarget; }
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51
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52 ScheduleHazardRecognizer *
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53 CreateTargetHazardRecognizer(const TargetMachine *TM,
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54 const ScheduleDAG *DAG) const;
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55
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56 ScheduleHazardRecognizer *
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57 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
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58 const ScheduleDAG *DAG) const;
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59
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60 // Branch analysis.
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61 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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62 MachineBasicBlock *&FBB,
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63 SmallVectorImpl<MachineOperand> &Cond,
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64 bool AllowModify = false) const;
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65 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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66 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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67 MachineBasicBlock *FBB,
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68 const SmallVectorImpl<MachineOperand> &Cond,
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69 DebugLoc DL) const;
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70
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71 virtual
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72 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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73
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74 // Predication support.
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75 bool isPredicated(const MachineInstr *MI) const;
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76
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77 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
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78 int PIdx = MI->findFirstPredOperandIdx();
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79 return PIdx != -1 ? (ARMCC::CondCodes)MI->getOperand(PIdx).getImm()
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80 : ARMCC::AL;
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81 }
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82
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83 virtual
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84 bool PredicateInstruction(MachineInstr *MI,
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85 const SmallVectorImpl<MachineOperand> &Pred) const;
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86
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87 virtual
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88 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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89 const SmallVectorImpl<MachineOperand> &Pred2) const;
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90
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91 virtual bool DefinesPredicate(MachineInstr *MI,
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92 std::vector<MachineOperand> &Pred) const;
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93
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94 virtual bool isPredicable(MachineInstr *MI) const;
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95
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96 /// GetInstSize - Returns the size of the specified MachineInstr.
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97 ///
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98 virtual unsigned GetInstSizeInBytes(const MachineInstr* MI) const;
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99
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100 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
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101 int &FrameIndex) const;
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102 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
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103 int &FrameIndex) const;
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104 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
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105 int &FrameIndex) const;
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106 virtual unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
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107 int &FrameIndex) const;
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108
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109 virtual void copyPhysReg(MachineBasicBlock &MBB,
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110 MachineBasicBlock::iterator I, DebugLoc DL,
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111 unsigned DestReg, unsigned SrcReg,
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112 bool KillSrc) const;
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113
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114 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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115 MachineBasicBlock::iterator MBBI,
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116 unsigned SrcReg, bool isKill, int FrameIndex,
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117 const TargetRegisterClass *RC,
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118 const TargetRegisterInfo *TRI) const;
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119
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120 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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121 MachineBasicBlock::iterator MBBI,
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122 unsigned DestReg, int FrameIndex,
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123 const TargetRegisterClass *RC,
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124 const TargetRegisterInfo *TRI) const;
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125
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126 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
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127
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128 virtual void reMaterialize(MachineBasicBlock &MBB,
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129 MachineBasicBlock::iterator MI,
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130 unsigned DestReg, unsigned SubIdx,
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131 const MachineInstr *Orig,
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132 const TargetRegisterInfo &TRI) const;
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133
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134 MachineInstr *duplicate(MachineInstr *Orig, MachineFunction &MF) const;
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135
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136 MachineInstr *commuteInstruction(MachineInstr*, bool=false) const;
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137
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138 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
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139 unsigned SubIdx, unsigned State,
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140 const TargetRegisterInfo *TRI) const;
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141
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142 virtual bool produceSameValue(const MachineInstr *MI0,
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143 const MachineInstr *MI1,
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144 const MachineRegisterInfo *MRI) const;
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145
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146 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
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147 /// determine if two loads are loading from the same base address. It should
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148 /// only return true if the base pointers are the same and the only
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149 /// differences between the two addresses is the offset. It also returns the
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150 /// offsets by reference.
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151 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
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152 int64_t &Offset1, int64_t &Offset2)const;
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153
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154 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
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155 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
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156 /// should be scheduled togther. On some targets if two loads are loading from
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157 /// addresses in the same cache line, it's better if they are scheduled
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158 /// together. This function takes two integers that represent the load offsets
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159 /// from the common base address. It returns true if it decides it's desirable
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160 /// to schedule the two loads together. "NumLoads" is the number of loads that
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161 /// have already been scheduled after Load1.
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162 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
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163 int64_t Offset1, int64_t Offset2,
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164 unsigned NumLoads) const;
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165
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166 virtual bool isSchedulingBoundary(const MachineInstr *MI,
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167 const MachineBasicBlock *MBB,
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168 const MachineFunction &MF) const;
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169
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170 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB,
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171 unsigned NumCycles, unsigned ExtraPredCycles,
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172 const BranchProbability &Probability) const;
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173
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174 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
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175 unsigned NumT, unsigned ExtraT,
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176 MachineBasicBlock &FMBB,
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177 unsigned NumF, unsigned ExtraF,
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178 const BranchProbability &Probability) const;
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179
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180 virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB,
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181 unsigned NumCycles,
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182 const BranchProbability
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183 &Probability) const {
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184 return NumCycles == 1;
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185 }
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186
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187 virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
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188 MachineBasicBlock &FMBB) const;
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189
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190 /// analyzeCompare - For a comparison instruction, return the source registers
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191 /// in SrcReg and SrcReg2 if having two register operands, and the value it
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192 /// compares against in CmpValue. Return true if the comparison instruction
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193 /// can be analyzed.
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194 virtual bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
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195 unsigned &SrcReg2, int &CmpMask,
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196 int &CmpValue) const;
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197
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198 /// optimizeCompareInstr - Convert the instruction to set the zero flag so
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199 /// that we can remove a "comparison with zero"; Remove a redundant CMP
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200 /// instruction if the flags can be updated in the same way by an earlier
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201 /// instruction such as SUB.
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202 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
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203 unsigned SrcReg2, int CmpMask, int CmpValue,
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204 const MachineRegisterInfo *MRI) const;
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205
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206 virtual bool analyzeSelect(const MachineInstr *MI,
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207 SmallVectorImpl<MachineOperand> &Cond,
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208 unsigned &TrueOp, unsigned &FalseOp,
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209 bool &Optimizable) const;
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210
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211 virtual MachineInstr *optimizeSelect(MachineInstr *MI, bool) const;
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212
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213 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
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214 /// instruction, try to fold the immediate into the use instruction.
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215 virtual bool FoldImmediate(MachineInstr *UseMI, MachineInstr *DefMI,
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216 unsigned Reg, MachineRegisterInfo *MRI) const;
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217
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218 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
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219 const MachineInstr *MI) const;
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220
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221 virtual
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222 int getOperandLatency(const InstrItineraryData *ItinData,
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223 const MachineInstr *DefMI, unsigned DefIdx,
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224 const MachineInstr *UseMI, unsigned UseIdx) const;
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225 virtual
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226 int getOperandLatency(const InstrItineraryData *ItinData,
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227 SDNode *DefNode, unsigned DefIdx,
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228 SDNode *UseNode, unsigned UseIdx) const;
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229
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230 /// VFP/NEON execution domains.
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231 std::pair<uint16_t, uint16_t>
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232 getExecutionDomain(const MachineInstr *MI) const;
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233 void setExecutionDomain(MachineInstr *MI, unsigned Domain) const;
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234
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235 unsigned getPartialRegUpdateClearance(const MachineInstr*, unsigned,
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236 const TargetRegisterInfo*) const;
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237 void breakPartialRegDependency(MachineBasicBlock::iterator, unsigned,
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238 const TargetRegisterInfo *TRI) const;
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239 /// Get the number of addresses by LDM or VLDM or zero for unknown.
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240 unsigned getNumLDMAddresses(const MachineInstr *MI) const;
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241
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242 private:
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243 unsigned getInstBundleLength(const MachineInstr *MI) const;
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244
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245 int getVLDMDefCycle(const InstrItineraryData *ItinData,
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246 const MCInstrDesc &DefMCID,
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247 unsigned DefClass,
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248 unsigned DefIdx, unsigned DefAlign) const;
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249 int getLDMDefCycle(const InstrItineraryData *ItinData,
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250 const MCInstrDesc &DefMCID,
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251 unsigned DefClass,
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252 unsigned DefIdx, unsigned DefAlign) const;
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253 int getVSTMUseCycle(const InstrItineraryData *ItinData,
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254 const MCInstrDesc &UseMCID,
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255 unsigned UseClass,
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256 unsigned UseIdx, unsigned UseAlign) const;
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257 int getSTMUseCycle(const InstrItineraryData *ItinData,
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258 const MCInstrDesc &UseMCID,
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259 unsigned UseClass,
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260 unsigned UseIdx, unsigned UseAlign) const;
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parents:
diff changeset
261 int getOperandLatency(const InstrItineraryData *ItinData,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
262 const MCInstrDesc &DefMCID,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
263 unsigned DefIdx, unsigned DefAlign,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
264 const MCInstrDesc &UseMCID,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
265 unsigned UseIdx, unsigned UseAlign) const;
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parents:
diff changeset
266
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parents:
diff changeset
267 unsigned getPredicationCost(const MachineInstr *MI) const;
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parents:
diff changeset
268
95c75e76d11b LLVM 3.4
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diff changeset
269 unsigned getInstrLatency(const InstrItineraryData *ItinData,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
270 const MachineInstr *MI,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
271 unsigned *PredCost = 0) const;
95c75e76d11b LLVM 3.4
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parents:
diff changeset
272
95c75e76d11b LLVM 3.4
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parents:
diff changeset
273 int getInstrLatency(const InstrItineraryData *ItinData,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
274 SDNode *Node) const;
95c75e76d11b LLVM 3.4
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diff changeset
275
95c75e76d11b LLVM 3.4
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diff changeset
276 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
277 const MachineRegisterInfo *MRI,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
278 const MachineInstr *DefMI, unsigned DefIdx,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
279 const MachineInstr *UseMI, unsigned UseIdx) const;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
280 bool hasLowDefLatency(const InstrItineraryData *ItinData,
95c75e76d11b LLVM 3.4
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parents:
diff changeset
281 const MachineInstr *DefMI, unsigned DefIdx) const;
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diff changeset
282
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diff changeset
283 /// verifyInstruction - Perform target specific instruction verification.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
284 bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const;
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parents:
diff changeset
285
95c75e76d11b LLVM 3.4
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parents:
diff changeset
286 private:
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
287 /// Modeling special VFP / NEON fp MLA / MLS hazards.
95c75e76d11b LLVM 3.4
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parents:
diff changeset
288
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diff changeset
289 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
290 /// MLx table.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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diff changeset
291 DenseMap<unsigned, unsigned> MLxEntryMap;
95c75e76d11b LLVM 3.4
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diff changeset
292
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diff changeset
293 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
294 /// stalls when scheduled together with fp MLA / MLS opcodes.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
295 SmallSet<unsigned, 16> MLxHazardOpcodes;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
296
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diff changeset
297 public:
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
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diff changeset
298 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
299 /// instruction.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
300 bool isFpMLxInstruction(unsigned Opcode) const {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
301 return MLxEntryMap.count(Opcode);
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
302 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
303
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
304 /// isFpMLxInstruction - This version also returns the multiply opcode and the
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
305 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
306 /// the MLX instructions with an extra lane operand.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
307 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
308 unsigned &AddSubOpc, bool &NegAcc,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
309 bool &HasLane) const;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
310
95c75e76d11b LLVM 3.4
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parents:
diff changeset
311 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
312 /// will cause stalls when scheduled after (within 4-cycle window) a fp
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
313 /// MLA / MLS instruction.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
314 bool canCauseFpMLxStall(unsigned Opcode) const {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
315 return MLxHazardOpcodes.count(Opcode);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
316 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
317
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parents:
diff changeset
318 /// Returns true if the instruction has a shift by immediate that can be
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
319 /// executed in one cycle less.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
320 bool isSwiftFastImmShift(const MachineInstr *MI) const;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
321 };
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
322
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
323 static inline
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
324 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
325 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
326 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
327
95c75e76d11b LLVM 3.4
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parents:
diff changeset
328 static inline
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
329 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
330 return MIB.addReg(0);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
331 }
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Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
332
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
333 static inline
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
334 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
335 bool isDead = false) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
336 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
337 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
338
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
339 static inline
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
340 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
341 return MIB.addReg(0);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
342 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
343
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
344 static inline
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
345 bool isUncondBranchOpcode(int Opc) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
346 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
347 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
348
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
349 static inline
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
350 bool isCondBranchOpcode(int Opc) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
351 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
352 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
353
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
354 static inline
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
355 bool isJumpTableBranchOpcode(int Opc) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
356 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd ||
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
357 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
358 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
359
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
360 static inline
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
361 bool isIndirectBranchOpcode(int Opc) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
362 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
363 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
364
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
365 static inline bool isPopOpcode(int Opc) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
366 return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
367 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
368 Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
369 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
370
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
371 static inline bool isPushOpcode(int Opc) {
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
372 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
373 Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
374 }
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
375
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
376 /// getInstrPredicate - If instruction is predicated, returns its predicate
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
377 /// condition, otherwise returns AL. It also returns the condition code
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
378 /// register by reference.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
379 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
380
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
381 int getMatchingCondBranchOpcode(int Opc);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
382
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
383 /// Determine if MI can be folded into an ARM MOVCC instruction, and return the
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
384 /// opcode of the SSA instruction representing the conditional MI.
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
385 unsigned canFoldARMInstrIntoMOVCC(unsigned Reg,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
386 MachineInstr *&MI,
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
387 const MachineRegisterInfo &MRI);
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
388
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
diff changeset
389 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
95c75e76d11b LLVM 3.4
Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
parents:
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390 /// the instruction is encoded with an 'S' bit is determined by the optional
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391 /// CPSR def operand.
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392 unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
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393
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394 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
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395 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
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396 /// code.
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397 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
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398 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
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399 unsigned DestReg, unsigned BaseReg, int NumBytes,
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400 ARMCC::CondCodes Pred, unsigned PredReg,
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401 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
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402
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403 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
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404 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
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405 unsigned DestReg, unsigned BaseReg, int NumBytes,
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406 ARMCC::CondCodes Pred, unsigned PredReg,
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407 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
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408 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
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409 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
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410 unsigned DestReg, unsigned BaseReg,
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411 int NumBytes, const TargetInstrInfo &TII,
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412 const ARMBaseRegisterInfo& MRI,
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413 unsigned MIFlags = 0);
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414
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415 /// Tries to add registers to the reglist of a given base-updating
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416 /// push/pop instruction to adjust the stack by an additional
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417 /// NumBytes. This can save a few bytes per function in code-size, but
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418 /// obviously generates more memory traffic. As such, it only takes
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419 /// effect in functions being optimised for size.
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420 bool tryFoldSPUpdateIntoPushPop(MachineFunction &MF, MachineInstr *MI,
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421 unsigned NumBytes);
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422
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423 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
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424 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
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425 /// offset could not be handled directly in MI, and return the left-over
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426 /// portion by reference.
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427 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
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428 unsigned FrameReg, int &Offset,
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429 const ARMBaseInstrInfo &TII);
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430
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431 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
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432 unsigned FrameReg, int &Offset,
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433 const ARMBaseInstrInfo &TII);
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434
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435 } // End llvm namespace
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436
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437 #endif