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annotate lib/Target/Mips/MipsInstrInfo.h @ 0:95c75e76d11b LLVM3.4

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LLVM 3.4
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Thu, 12 Dec 2013 13:56:28 +0900
parents
children 54457678186b
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0
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1 //===-- MipsInstrInfo.h - Mips Instruction Information ----------*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file contains the Mips implementation of the TargetInstrInfo class.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #ifndef MIPSINSTRUCTIONINFO_H
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15 #define MIPSINSTRUCTIONINFO_H
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16
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17 #include "Mips.h"
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18 #include "MipsAnalyzeImmediate.h"
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19 #include "MipsRegisterInfo.h"
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20 #include "llvm/CodeGen/MachineInstrBuilder.h"
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21 #include "llvm/Support/ErrorHandling.h"
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22 #include "llvm/Target/TargetInstrInfo.h"
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23
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24 #define GET_INSTRINFO_HEADER
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25 #include "MipsGenInstrInfo.inc"
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26
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27 namespace llvm {
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28
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29 class MipsInstrInfo : public MipsGenInstrInfo {
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30 virtual void anchor();
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31 protected:
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32 MipsTargetMachine &TM;
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33 unsigned UncondBrOpc;
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34
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35 public:
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36 enum BranchType {
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37 BT_None, // Couldn't analyze branch.
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38 BT_NoBranch, // No branches found.
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39 BT_Uncond, // One unconditional branch.
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40 BT_Cond, // One conditional branch.
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41 BT_CondUncond, // A conditional branch followed by an unconditional branch.
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42 BT_Indirect // One indirct branch.
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43 };
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44
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45 explicit MipsInstrInfo(MipsTargetMachine &TM, unsigned UncondBrOpc);
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46
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47 static const MipsInstrInfo *create(MipsTargetMachine &TM);
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48
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49 /// Branch Analysis
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50 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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51 MachineBasicBlock *&FBB,
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52 SmallVectorImpl<MachineOperand> &Cond,
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53 bool AllowModify) const;
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54
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55 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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56
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57 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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58 MachineBasicBlock *FBB,
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59 const SmallVectorImpl<MachineOperand> &Cond,
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60 DebugLoc DL) const;
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61
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62 virtual
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63 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
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64
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65 BranchType AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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66 MachineBasicBlock *&FBB,
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67 SmallVectorImpl<MachineOperand> &Cond,
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68 bool AllowModify,
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69 SmallVectorImpl<MachineInstr*> &BranchInstrs) const;
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70
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71 /// Insert nop instruction when hazard condition is found
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72 virtual void insertNoop(MachineBasicBlock &MBB,
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73 MachineBasicBlock::iterator MI) const;
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74
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75 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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76 /// such, whenever a client has an instance of instruction info, it should
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77 /// always be able to get register info as well (through this method).
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78 ///
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79 virtual const MipsRegisterInfo &getRegisterInfo() const = 0;
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80
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81 virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;
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82
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83 /// Return the number of bytes of code the specified instruction may be.
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84 unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
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85
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86 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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87 MachineBasicBlock::iterator MBBI,
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88 unsigned SrcReg, bool isKill, int FrameIndex,
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89 const TargetRegisterClass *RC,
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90 const TargetRegisterInfo *TRI) const {
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91 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0);
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92 }
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93
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94 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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95 MachineBasicBlock::iterator MBBI,
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96 unsigned DestReg, int FrameIndex,
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97 const TargetRegisterClass *RC,
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98 const TargetRegisterInfo *TRI) const {
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99 loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
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100 }
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101
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102 virtual void storeRegToStack(MachineBasicBlock &MBB,
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103 MachineBasicBlock::iterator MI,
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104 unsigned SrcReg, bool isKill, int FrameIndex,
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105 const TargetRegisterClass *RC,
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106 const TargetRegisterInfo *TRI,
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107 int64_t Offset) const = 0;
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108
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109 virtual void loadRegFromStack(MachineBasicBlock &MBB,
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110 MachineBasicBlock::iterator MI,
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111 unsigned DestReg, int FrameIndex,
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112 const TargetRegisterClass *RC,
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113 const TargetRegisterInfo *TRI,
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114 int64_t Offset) const = 0;
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115
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116 /// Create an instruction which has the same operands and memory operands
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117 /// as MI but has a new opcode.
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118 MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
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119 MachineBasicBlock::iterator I) const;
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120
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121 protected:
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122 bool isZeroImm(const MachineOperand &op) const;
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123
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124 MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI,
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125 unsigned Flag) const;
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126
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127 private:
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128 virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0;
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129
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130 void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
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131 MachineBasicBlock *&BB,
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132 SmallVectorImpl<MachineOperand> &Cond) const;
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133
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134 void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, DebugLoc DL,
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135 const SmallVectorImpl<MachineOperand>& Cond) const;
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136 };
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137
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138 /// Create MipsInstrInfo objects.
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139 const MipsInstrInfo *createMips16InstrInfo(MipsTargetMachine &TM);
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140 const MipsInstrInfo *createMipsSEInstrInfo(MipsTargetMachine &TM);
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141
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142 }
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143
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144 #endif