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annotate lib/Target/SystemZ/README.txt @ 0:95c75e76d11b LLVM3.4

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LLVM 3.4
author Kaito Tokumori <e105711@ie.u-ryukyu.ac.jp>
date Thu, 12 Dec 2013 13:56:28 +0900
parents
children e4204d083e25
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1 //===---------------------------------------------------------------------===//
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2 // Random notes about and ideas for the SystemZ backend.
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3 //===---------------------------------------------------------------------===//
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4
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5 The initial backend is deliberately restricted to z10. We should add support
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6 for later architectures at some point.
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7
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8 --
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9
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10 SystemZDAGToDAGISel::SelectInlineAsmMemoryOperand() is passed "m" for all
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11 inline asm memory constraints; it doesn't get to see the original constraint.
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12 This means that it must conservatively treat all inline asm constraints
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13 as the most restricted type, "R".
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14
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15 --
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16
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17 If an inline asm ties an i32 "r" result to an i64 input, the input
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18 will be treated as an i32, leaving the upper bits uninitialised.
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19 For example:
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20
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21 define void @f4(i32 *%dst) {
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22 %val = call i32 asm "blah $0", "=r,0" (i64 103)
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23 store i32 %val, i32 *%dst
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24 ret void
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25 }
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26
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27 from CodeGen/SystemZ/asm-09.ll will use LHI rather than LGHI.
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28 to load 103. This seems to be a general target-independent problem.
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29
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30 --
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31
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32 The tuning of the choice between LOAD ADDRESS (LA) and addition in
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33 SystemZISelDAGToDAG.cpp is suspect. It should be tweaked based on
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34 performance measurements.
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35
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36 --
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37
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38 There is no scheduling support.
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39
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40 --
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41
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42 We don't use the BRANCH ON INDEX instructions.
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43
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44 --
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45
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46 We might want to use BRANCH ON CONDITION for conditional indirect calls
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47 and conditional returns.
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48
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49 --
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50
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51 We don't use the TEST DATA CLASS instructions.
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52
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53 --
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54
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55 We could use the generic floating-point forms of LOAD COMPLEMENT,
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56 LOAD NEGATIVE and LOAD POSITIVE in cases where we don't need the
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57 condition codes. For example, we could use LCDFR instead of LCDBR.
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58
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59 --
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60
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61 We only use MVC, XC and CLC for constant-length block operations.
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62 We could extend them to variable-length operations too,
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63 using EXECUTE RELATIVE LONG.
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64
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65 MVCIN, MVCLE and CLCLE may be worthwhile too.
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66
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67 --
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68
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69 We don't use CUSE or the TRANSLATE family of instructions for string
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70 operations. The TRANSLATE ones are probably more difficult to exploit.
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71
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72 --
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73
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74 We don't take full advantage of builtins like fabsl because the calling
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75 conventions require f128s to be returned by invisible reference.
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76
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77 --
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78
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79 ADD LOGICAL WITH SIGNED IMMEDIATE could be useful when we need to
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80 produce a carry. SUBTRACT LOGICAL IMMEDIATE could be useful when we
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81 need to produce a borrow. (Note that there are no memory forms of
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82 ADD LOGICAL WITH CARRY and SUBTRACT LOGICAL WITH BORROW, so the high
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83 part of 128-bit memory operations would probably need to be done
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84 via a register.)
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85
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86 --
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87
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88 We don't use the halfword forms of LOAD REVERSED and STORE REVERSED
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89 (LRVH and STRVH).
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90
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91 --
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92
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93 We don't use ICM or STCM.
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94
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95 --
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96
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97 DAGCombiner doesn't yet fold truncations of extended loads. Functions like:
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98
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99 unsigned long f (unsigned long x, unsigned short *y)
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100 {
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101 return (x << 32) | *y;
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102 }
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103
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104 therefore end up as:
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105
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106 sllg %r2, %r2, 32
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107 llgh %r0, 0(%r3)
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108 lr %r2, %r0
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109 br %r14
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110
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111 but truncating the load would give:
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112
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113 sllg %r2, %r2, 32
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114 lh %r2, 0(%r3)
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115 br %r14
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116
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117 --
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118
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119 Functions like:
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120
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121 define i64 @f1(i64 %a) {
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122 %and = and i64 %a, 1
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123 ret i64 %and
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124 }
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125
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126 ought to be implemented as:
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127
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128 lhi %r0, 1
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129 ngr %r2, %r0
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130 br %r14
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131
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132 but two-address optimisations reverse the order of the AND and force:
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133
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134 lhi %r0, 1
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135 ngr %r0, %r2
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136 lgr %r2, %r0
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137 br %r14
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138
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139 CodeGen/SystemZ/and-04.ll has several examples of this.
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140
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141 --
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142
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143 Out-of-range displacements are usually handled by loading the full
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144 address into a register. In many cases it would be better to create
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145 an anchor point instead. E.g. for:
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146
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147 define void @f4a(i128 *%aptr, i64 %base) {
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148 %addr = add i64 %base, 524288
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149 %bptr = inttoptr i64 %addr to i128 *
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150 %a = load volatile i128 *%aptr
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151 %b = load i128 *%bptr
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152 %add = add i128 %a, %b
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153 store i128 %add, i128 *%aptr
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154 ret void
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155 }
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156
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157 (from CodeGen/SystemZ/int-add-08.ll) we load %base+524288 and %base+524296
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158 into separate registers, rather than using %base+524288 as a base for both.
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159
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160 --
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161
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162 Dynamic stack allocations round the size to 8 bytes and then allocate
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163 that rounded amount. It would be simpler to subtract the unrounded
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164 size from the copy of the stack pointer and then align the result.
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165 See CodeGen/SystemZ/alloca-01.ll for an example.
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166
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167 --
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168
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169 Atomic loads and stores use the default compare-and-swap based implementation.
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170 This is much too conservative in practice, since the architecture guarantees
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171 that 1-, 2-, 4- and 8-byte loads and stores to aligned addresses are
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172 inherently atomic.
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173
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174 --
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175
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176 If needed, we can support 16-byte atomics using LPQ, STPQ and CSDG.
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177
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178 --
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179
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180 We might want to model all access registers and use them to spill
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181 32-bit values.