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1 //===- LanaiInstrInfo.h - Lanai Instruction Information ---------*- C++ -*-===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // This file contains the Lanai implementation of the TargetInstrInfo class.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #ifndef LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H
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15 #define LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H
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16
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17 #include "LanaiRegisterInfo.h"
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134
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18 #include "llvm/CodeGen/TargetInstrInfo.h"
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120
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19
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20 #define GET_INSTRINFO_HEADER
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21 #include "LanaiGenInstrInfo.inc"
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22
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23 namespace llvm {
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24
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25 class LanaiInstrInfo : public LanaiGenInstrInfo {
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26 const LanaiRegisterInfo RegisterInfo;
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27
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28 public:
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29 LanaiInstrInfo();
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30
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31 // getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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32 // such, whenever a client has an instance of instruction info, it should
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33 // always be able to get register info as well (through this method).
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34 virtual const LanaiRegisterInfo &getRegisterInfo() const {
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35 return RegisterInfo;
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36 }
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37
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38 bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
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39 AliasAnalysis *AA) const override;
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40
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41 unsigned isLoadFromStackSlot(const MachineInstr &MI,
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42 int &FrameIndex) const override;
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43
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44 unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
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45 int &FrameIndex) const override;
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46
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47 unsigned isStoreToStackSlot(const MachineInstr &MI,
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48 int &FrameIndex) const override;
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49
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50 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position,
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51 const DebugLoc &DL, unsigned DestinationRegister,
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52 unsigned SourceRegister, bool KillSource) const override;
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53
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54 void
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55 storeRegToStackSlot(MachineBasicBlock &MBB,
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56 MachineBasicBlock::iterator Position,
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57 unsigned SourceRegister, bool IsKill, int FrameIndex,
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58 const TargetRegisterClass *RegisterClass,
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59 const TargetRegisterInfo *RegisterInfo) const override;
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60
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61 void
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62 loadRegFromStackSlot(MachineBasicBlock &MBB,
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63 MachineBasicBlock::iterator Position,
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64 unsigned DestinationRegister, int FrameIndex,
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65 const TargetRegisterClass *RegisterClass,
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66 const TargetRegisterInfo *RegisterInfo) const override;
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67
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68 bool expandPostRAPseudo(MachineInstr &MI) const override;
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69
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70 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
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71 int64_t &Offset,
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72 const TargetRegisterInfo *TRI) const override;
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73
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74 bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg,
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75 int64_t &Offset, unsigned &Width,
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76 const TargetRegisterInfo *TRI) const;
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77
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78 std::pair<unsigned, unsigned>
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79 decomposeMachineOperandsTargetFlags(unsigned TF) const override;
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80
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81 ArrayRef<std::pair<unsigned, const char *>>
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82 getSerializableDirectMachineOperandTargetFlags() const override;
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83
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84 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TrueBlock,
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85 MachineBasicBlock *&FalseBlock,
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86 SmallVectorImpl<MachineOperand> &Condition,
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87 bool AllowModify) const override;
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88
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89 unsigned removeBranch(MachineBasicBlock &MBB,
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90 int *BytesRemoved = nullptr) const override;
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91
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92 // For a comparison instruction, return the source registers in SrcReg and
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93 // SrcReg2 if having two register operands, and the value it compares against
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94 // in CmpValue. Return true if the comparison instruction can be analyzed.
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95 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
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96 unsigned &SrcReg2, int &CmpMask,
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97 int &CmpValue) const override;
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98
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99 // See if the comparison instruction can be converted into something more
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100 // efficient. E.g., on Lanai register-register instructions can set the flag
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101 // register, obviating the need for a separate compare.
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102 bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
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103 unsigned SrcReg2, int CmpMask, int CmpValue,
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104 const MachineRegisterInfo *MRI) const override;
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105
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106 // Analyze the given select instruction, returning true if it cannot be
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107 // understood. It is assumed that MI->isSelect() is true.
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108 //
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109 // When successful, return the controlling condition and the operands that
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110 // determine the true and false result values.
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111 //
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112 // Result = SELECT Cond, TrueOp, FalseOp
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113 //
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114 // Lanai can optimize certain select instructions, for example by predicating
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115 // the instruction defining one of the operands and sets Optimizable to true.
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116 bool analyzeSelect(const MachineInstr &MI,
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117 SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
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118 unsigned &FalseOp, bool &Optimizable) const override;
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119
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120 // Given a select instruction that was understood by analyzeSelect and
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121 // returned Optimizable = true, attempt to optimize MI by merging it with one
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122 // of its operands. Returns NULL on failure.
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123 //
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124 // When successful, returns the new select instruction. The client is
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125 // responsible for deleting MI.
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126 //
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127 // If both sides of the select can be optimized, the TrueOp is modifed.
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128 // PreferFalse is not used.
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129 MachineInstr *optimizeSelect(MachineInstr &MI,
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130 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
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131 bool PreferFalse) const override;
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132
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133 bool reverseBranchCondition(
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134 SmallVectorImpl<MachineOperand> &Condition) const override;
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135
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136 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TrueBlock,
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137 MachineBasicBlock *FalseBlock,
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138 ArrayRef<MachineOperand> Condition,
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139 const DebugLoc &DL,
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140 int *BytesAdded = nullptr) const override;
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141 };
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142
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143 static inline bool isSPLSOpcode(unsigned Opcode) {
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144 switch (Opcode) {
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145 case Lanai::LDBs_RI:
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146 case Lanai::LDBz_RI:
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147 case Lanai::LDHs_RI:
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148 case Lanai::LDHz_RI:
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149 case Lanai::STB_RI:
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150 case Lanai::STH_RI:
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151 return true;
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152 default:
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153 return false;
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154 }
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155 }
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156
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157 static inline bool isRMOpcode(unsigned Opcode) {
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158 switch (Opcode) {
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159 case Lanai::LDW_RI:
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160 case Lanai::SW_RI:
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161 return true;
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162 default:
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163 return false;
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164 }
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165 }
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166
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167 static inline bool isRRMOpcode(unsigned Opcode) {
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168 switch (Opcode) {
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169 case Lanai::LDBs_RR:
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170 case Lanai::LDBz_RR:
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171 case Lanai::LDHs_RR:
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172 case Lanai::LDHz_RR:
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173 case Lanai::LDWz_RR:
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174 case Lanai::LDW_RR:
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175 case Lanai::STB_RR:
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176 case Lanai::STH_RR:
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177 case Lanai::SW_RR:
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178 return true;
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179 default:
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180 return false;
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181 }
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182 }
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183
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184 } // namespace llvm
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185
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186 #endif // LLVM_LIB_TARGET_LANAI_LANAIINSTRINFO_H
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