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1 //===-- LanaiTargetMachine.cpp - Define TargetMachine for Lanai ---------===//
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2 //
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3 // The LLVM Compiler Infrastructure
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4 //
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5 // This file is distributed under the University of Illinois Open Source
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6 // License. See LICENSE.TXT for details.
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7 //
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8 //===----------------------------------------------------------------------===//
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9 //
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10 // Implements the info about Lanai target spec.
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11 //
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12 //===----------------------------------------------------------------------===//
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13
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14 #include "LanaiTargetMachine.h"
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15
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16 #include "Lanai.h"
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17 #include "LanaiTargetObjectFile.h"
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18 #include "LanaiTargetTransformInfo.h"
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19 #include "llvm/Analysis/TargetTransformInfo.h"
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20 #include "llvm/CodeGen/Passes.h"
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21 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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22 #include "llvm/CodeGen/TargetPassConfig.h"
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23 #include "llvm/Support/FormattedStream.h"
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24 #include "llvm/Support/TargetRegistry.h"
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25 #include "llvm/Target/TargetOptions.h"
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26
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27 using namespace llvm;
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28
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29 namespace llvm {
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30 void initializeLanaiMemAluCombinerPass(PassRegistry &);
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31 } // namespace llvm
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32
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33 extern "C" void LLVMInitializeLanaiTarget() {
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34 // Register the target.
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35 RegisterTargetMachine<LanaiTargetMachine> registered_target(
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36 getTheLanaiTarget());
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37 }
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38
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39 static std::string computeDataLayout() {
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40 // Data layout (keep in sync with clang/lib/Basic/Targets.cpp)
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41 return "E" // Big endian
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42 "-m:e" // ELF name manging
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43 "-p:32:32" // 32-bit pointers, 32 bit aligned
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44 "-i64:64" // 64 bit integers, 64 bit aligned
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45 "-a:0:32" // 32 bit alignment of objects of aggregate type
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46 "-n32" // 32 bit native integer width
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47 "-S64"; // 64 bit natural stack alignment
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48 }
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49
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50 static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
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51 if (!RM.hasValue())
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52 return Reloc::PIC_;
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53 return *RM;
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54 }
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55
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56 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
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57 if (CM)
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58 return *CM;
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59 return CodeModel::Medium;
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60 }
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61
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62 LanaiTargetMachine::LanaiTargetMachine(const Target &T, const Triple &TT,
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63 StringRef Cpu, StringRef FeatureString,
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64 const TargetOptions &Options,
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65 Optional<Reloc::Model> RM,
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66 Optional<CodeModel::Model> CodeModel,
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67 CodeGenOpt::Level OptLevel, bool JIT)
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68 : LLVMTargetMachine(T, computeDataLayout(), TT, Cpu, FeatureString, Options,
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69 getEffectiveRelocModel(RM),
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70 getEffectiveCodeModel(CodeModel), OptLevel),
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71 Subtarget(TT, Cpu, FeatureString, *this, Options, getCodeModel(),
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72 OptLevel),
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73 TLOF(new LanaiTargetObjectFile()) {
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74 initAsmInfo();
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75 }
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76
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134
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77 TargetTransformInfo
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78 LanaiTargetMachine::getTargetTransformInfo(const Function &F) {
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79 return TargetTransformInfo(LanaiTTIImpl(this, F));
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120
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80 }
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81
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82 namespace {
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83 // Lanai Code Generator Pass Configuration Options.
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84 class LanaiPassConfig : public TargetPassConfig {
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85 public:
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86 LanaiPassConfig(LanaiTargetMachine &TM, PassManagerBase *PassManager)
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120
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87 : TargetPassConfig(TM, *PassManager) {}
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88
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89 LanaiTargetMachine &getLanaiTargetMachine() const {
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90 return getTM<LanaiTargetMachine>();
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91 }
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92
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93 bool addInstSelector() override;
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94 void addPreSched2() override;
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95 void addPreEmitPass() override;
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96 };
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97 } // namespace
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98
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99 TargetPassConfig *
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100 LanaiTargetMachine::createPassConfig(PassManagerBase &PassManager) {
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101 return new LanaiPassConfig(*this, &PassManager);
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102 }
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103
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104 // Install an instruction selector pass.
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105 bool LanaiPassConfig::addInstSelector() {
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106 addPass(createLanaiISelDag(getLanaiTargetMachine()));
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107 return false;
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108 }
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109
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110 // Implemented by targets that want to run passes immediately before
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111 // machine code is emitted.
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112 void LanaiPassConfig::addPreEmitPass() {
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113 addPass(createLanaiDelaySlotFillerPass(getLanaiTargetMachine()));
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114 }
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115
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116 // Run passes after prolog-epilog insertion and before the second instruction
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117 // scheduling pass.
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118 void LanaiPassConfig::addPreSched2() {
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119 addPass(createLanaiMemAluCombinerPass());
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120 }
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